非對稱金氧半場效電晶體及無接面多晶矽薄膜電晶體的研究

Abstract

在本論文中，我們利用傳統I-line步進機發展一新穎雙重微影技術，可將閘極長度微縮至80奈米；而後改良此雙重微影製程可進一步縮小其線寬以製作出次60奈米線寬圖形，並將之用於45奈米n型通道金氧半場效電晶體的製作。此技術與一般大學實驗室常用的方法，例如電子束直寫系統與光阻灰化技術進行比較，包括臨界尺寸(CD)均勻性、產率、線邊緣粗糙度(LER)、最小線寬等特性，作定量上的比較。憑藉所提出的I-line雙重微影技術，我們也研製出對稱與非對稱源汲極元件，並討論其電性特性與相關的可靠度議題。 我們發現，雖然對稱暈邊(halo)結構相較於對照組能有效降低104倍次臨界漏電及改善短通道效應，但同時造成嚴重的逆短通道效應與犧牲25%電流驅動力。為了改善這項缺失，我們提出非對稱暈邊結構製程以解決上述的矛盾。相較於對稱暈邊結構，非對稱暈邊結構貢獻了7.8% 的轉導增益以及 15%電流驅動力增益另外在可靠度議題方面，我們發現暈邊掺雜會增加在閘極邊緣下汲極的側向電場強度，進而使熱載子退化效應變得更嚴重。藉由非對稱暈邊結構，我們可以減緩熱載子退化效應，其臨界電壓偏移為0.21伏特，對稱式結構則為0.32伏特的臨界電壓偏移。此外，我們也藉由探討熱載子測試前後的閃爍雜訊特性來評估暈邊掺雜對元件的影響，發現汲極端暈邊掺雜也會造成元件雜訊劣化。 另一方面，我們研製出各式不需佈植製程的無接面元件，包含多閘極組態奈 ii 米線場效電晶體、三維多層堆疊奈米線場效電晶體、多閘極組態奈米線SONOS記憶體元件、以及平面式薄膜電晶體以探討其操作機制。藉由導入臨場磷摻雜多晶矽薄膜作為上述無接面元件的通道及源汲極材料以實現無佈植技術的製程方式。由無接面奈米線場效電晶體的電性結果發現，足夠小的奈米線通道截面對於關閉n型重摻雜通道與得到優異電流開關比值(在閘極電壓為 2 伏特下有5.2 × 106倍)是非常重要的。此外，由於較低的源汲極串聯阻值與通道阻值，無接面元件具有較高的電流驅動表現約為反轉式元件的1.75倍。 接下來，相較於反轉式元件而言，無接面奈米線SONOS記憶體元件展現較快的寫入速度與不錯的資料保存能力，而相當的抹除速度與毫不遜色的記憶窗口也被記錄。另一方面，摻雜濃度與閘極組態對於無接面記憶體元件的效應也一併探討。由電性與記憶體特性結果發現對於高性能SONOS應用方面而言，無接面多晶矽奈米線記憶體元件的摻雜濃度必須謹慎的調整。簡而言之，就低成本與極高密度非揮發記憶體應用而言，所提出的無接面奈米線SONOS技術是相當有潛力的。 最後，我們研製n型平面式超薄型無接面多晶矽薄膜電晶體以探討對射頻與低頻雜訊之影響。在汲極電壓2伏特偏壓下無接面元件展現出優異的截止頻率(3.36 GHz)與最大共振頻率(7.37 GHz)以實現低電壓操作的應用。在低頻雜訊方面，相較於對照組的反轉式元件，無接面元件改善了低頻雜訊以及達到較高的信號雜訊比。此外，我們也建立了無接面元件的小訊號模型並且對照實驗與模擬結果以驗證其準確性，由對照的結果發現所建立的小訊號模型是成功運作的。

In this dissertation, we have developed a novel double-patterning (DP) technique for generation of gate patterns with gate length down to 80 nm using only a conventional I-line stepper. With a modification in the process steps, this DP technique can further shrink the patterns down below sub-60 nm and have been employed to fabricate 45nm nMOSFETs. This technique is also compared with alternative methods, such as electron-beam direct writing and photoresist-ashing scheme which are often adopted in the university-based laboratories, from the perspectives of the uniformity of critical dimension (CD), throughput, line edge roughness (LER), and minimum line width. Moreover, with the aid of the proposed I-line DP technique, several symmetrical or asymmetrical S/D devices were fabricated and characterized. We found that, although the symmetrical halo-doping structure helps reduce the subthreshold leakage by four orders of magnitude over the control and improve the short-channel effects (SCEs), severe reverse-short-channel effect (RSCE) and degenerate current drivability (25% output current degradation as compared with the control) are compromised at the same time. To address this issue, the implementation of asymmetrical halo structure was proposed to relieve such a dilemma. In contrast with symmetrical halo structure, the Asymmetric Halo split shows a 7.8% higher transconductance and a 15% larger driving current. For reliability issue, we found that the drain-side halo doping is the primary culprit of hot-carrier (HC) degradation due to the increased peak lateral electric field. The aggravation of HC degradation is alleviated with the Asymmetric Halo split, while the Symmetric Halo split exhibits threshold iv voltage shift of 0.32 V and the Asymmetric Halo split performs that of 0.21 V after 5000-second of hot-electron stressing. Furthermore, we have evaluated the impact of halo on device performance by investigating the flicker noise (1/f) characteristics before and after the hot-carrier stress, indicating that drain-side halo doping. deteriorates low-frequency noise as well. Concurrently, we have fabricated and characterized junctionless (JL) polycrystalline silicon-based thin-film transistors (TFTs) of various configuration, including multiple-gated nanowire (NW) field-effect transistors (FETs), 3-D multilayer-stacked NWFETs, multiple-gated NW silicon–oxide–nitride–oxide–silicon (SONOS) memory cells, and planar TFTs with an implant-free technique. The results indicate that a sufficiently small cross section of the channel, less than 20 nm × 20 nm, is essential to switch off the device and obtain a superior on-to-off current ratio of 5.2 × 106 at VG = 2 V. Moreover, JL devices exhibit boosted on-state behavior (a 1.75 times output current value over the inversion-mode counterpart), as ascribed to lower S/D series resistances and channel resistances. The fabricated NW SONOS memory devices with JL scheme depict faster programming speed and better data retention behavior, while a comparable erase window and similar erasing efficiency to the inversion-mode (IM) counterparts are also observed. On the other hand, the effects of doping concentration and gate configuration implemented with JL scheme have also been investigated. From the results of the electrical characterizations and memory properties, the doping concentration of the JL poly-Si NW device should be carefully optimized for high-performance SONOS applications. We’ve also fabricated and characterized n-type planar ultrathin JL poly-Si TFTs with emphasis on RF and low-frequency noise (LFN) performance. The 0.2-μm JL device shows remarkable ft and fmax of 3.36 and 7.37 GHz, respectively, at a VD of 2 V. In addition, the JL devices improve the LFN and achieves higher signal-to-noise ratio as compared with those of the IM devices. Finally, we have derived a small-signal model for the fabricated JL devices and verified its accuracy by comparing the S-parameters.