High-Voltage nLDMOS in Waffle-Layout Style With Body-Injected Technique for ESD Protection

doi:10.1109/LED.2009.2013368

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chen, Wen-Yi	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.date.accessioned	2014-12-08T15:09:42Z	-
dc.date.available	2014-12-08T15:09:42Z	-
dc.date.issued	2009-04-01	en_US
dc.identifier.issn	0741-3106	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/LED.2009.2013368	en_US
dc.identifier.uri	http://hdl.handle.net/11536/7419	-
dc.description.abstract	Electrostatic-discharge robustness of n-channel lateral DMOS (nLDMOS) has been significantly Increased in this letter through the waffle-layout style with body-current Injection. This body-injected technique on high-voltage nLDMOS has been successfully verified in a 0.5-mu m 16-V bipolar CMOS DMOS process without additional process or mask modification. The TLP-measured results confirmed that the secondary breakdown current (I(t2)) of nLDMOS has a more than 2x increase by the body-current injection.	en_US
dc.language.iso	en_US	en_US
dc.subject	Bipolar CMOS DMOS (BCD) process	en_US
dc.subject	body-current injection	en_US
dc.subject	electrostatic discharge (ESD)	en_US
dc.subject	lateral DMOS (LDMOS)	en_US
dc.title	High-Voltage nLDMOS in Waffle-Layout Style With Body-Injected Technique for ESD Protection	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/LED.2009.2013368	en_US
dc.identifier.journal	IEEE ELECTRON DEVICE LETTERS	en_US
dc.citation.volume	30	en_US
dc.citation.issue	4	en_US
dc.citation.spage	389	en_US
dc.citation.epage	391	en_US
dc.contributor.department	電機學院	zh_TW
dc.contributor.department	College of Electrical and Computer Engineering	en_US
dc.identifier.wosnumber	WOS:000264629100026	-
dc.citation.woscount	4	-
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