具有輕掺雜汲極之複晶矽薄膜電晶體電性模型建立

Abstract

複晶矽薄膜電晶體在面板技術的應用上，由於其具有高遷移率，可以實現系統面板(System on Panel)的技術，也就是可以將周邊電路直接以複晶矽薄膜電晶體實現在玻璃基板上，與面板矩陣電路結合成所謂的系統面板。然而，在這樣的技術發展中，準確的元件模型是SPICE tool中最重要的基礎，在本論文中，我們特別針對具有輕摻雜汲極(Lightly-Doped Drain, LDD)結構之N型低溫複晶矽薄膜電晶體建立DC電性模型。 首先，我們研究輕摻雜汲極寄生電阻的萃取方法。利用變化不同的通道長度和不同的輕摻雜汲極長度，可以萃取出不同的寄生電阻。然後我們建立包含寄生電阻效應的元件等效電路，根據等效電路，推導出元件的電性模型。模型產生的電性，可以準確描述元件在通道長度6 □m - 30 □m以及LDD長度0 □m - 3 □m的輸出特性。除了基本的電流輸出特性，我們也分析元件的轉導特性以及輸出阻抗特性在不同偏壓下的變化，並利用前述的模型解釋寄生阻抗所造成的影響；另外，由於複晶矽薄膜特有的DIGBL(Drain-Induced Grain Barrier Lowering)效應，LDD區域的阻抗效應其實會在LDD長度越長通道長度越短的狀況下影響到元件的線性區特性，我們也針對LDD結構在不同偏壓下的等效阻抗變化做了初步的模型；最後，我們並結合了元件在變溫量測下定義出的晶粒邊界位障，成功建立了包含薄膜差異性、元件LDD結構差異對元件特性影響的模型。

To realize the system-on-panel (SOP) technology, in which we combine the peripheral circuit and panel array circuit on the same glass substrate, it is essential to develop accurate device I-V model for Poly-Si TFTs. In this thesis, we especially focus on the modeling of n-channel devices with LDD(Lightly-Doped Drain) structure. Firstly, parasitic resistance parameters were extracted from devices with various channel length and LDD length. Then, the device equivalent circuit had been developed including the extracted parasitic resistance parameters. An accurate I-V model was established by combining basic TFT model and the parasitic resistance effects. The model had been verified for devices with channel length varied from 6 □m to 30 □m. The transconductance and output resistance behavior are also well explained by our proposed model. The special DIGBL effect of poly-Si film is also observed when the devices with large LDD length and short channel length. We used testkey structure to clarify this effect and established adequate model to explain this phenomena. Finally, the model was combined with the grain barrier height model by extracted the grain barrier height from the Arrenhius plot. Good agreements are found when comparing the simulated results and the experimental results.