低電壓互補式金氧半導體高頻壓控振盪器與鎖相迴路設計

Abstract

無線通訊射頻晶片在收發機的應用裡，低功率消耗為一個重要的課題，本論文以壓控振盪器與鎖相迴路兩個部份來探討低電壓操作的電路設計，藉以降低功率消耗，並利用TSMC 0.18μm RF CMOS製程完成可應用於超寬頻UWB系統之低電壓CMOS高頻壓控振盪器與鎖相迴路電路和WiFi系統的低電壓CMOS雙頻段壓控振盪器設計。 第一部份設計三種不同電路特性的低電壓壓控振盪器；第一個設計為應用於超寬頻0.6V低電壓之壓控振盪器，採用NMOS 交連耦合對的LC調諧壓控振盪器加上交聯電容架構設計，藉由在主動埠並聯電容改善品質因數。量測結果，功率消耗僅有0.54mW，FOM值為185。第二個振盪器採用四相位正交輸出的設計，利用基底改良雜訊的方式，改善一般低電壓正交輸出壓控振盪器的相位雜訊率，在0.65V操作下量測功率消耗為2.67mW， FOM值為181.7。第三個振盪器為雙頻段四相位正交輸出的設計，利用簡化雙頻帶VCO及電流再利用方式設計，降低一般雙頻段正交輸出壓控振盪器耗功率的缺點。在低頻段1.3V及高頻段1.5V電壓操作下，量測功率消耗為5.46mW及6.75mW，FOM值皆為171。 第二部份設計可應用於超寬頻UWB系統之低電壓鎖相迴路。鎖相迴路設計在1V的低電壓操作，輸出頻率為5.016GHz，採用的除頻器為使用位準偏移的主樸式偶合閘(CML divider)電路，配合預先充放電式的相位比較器，改良單相時脈除頻器(TSPC divider)的設計，整個迴路模擬結果功率消耗為5.58mW。

The low power consumption plays an important role in RFIC’s for wireless communication transceiver. RFIC usually consists of Mixer, Voltage-Controlled Oscillator (VCO), Filter, Power Amplifier, etc. One of important component is VCO in power consumption issue. In this thesis a low voltage operation circuit for VCO and Phase-Locked Loop (PLL) is developed. The TSMC 0.18μm RF CMOS manufacture Technology is used for ultra low voltage VCO and low voltage phase-locked loop which can be applied to UWB system and dual band quadrature phase voltage-controlled oscillator which can be applied to WiFi system. There are three kinds of low voltage VCOs be implemented with different circuit characteristics. The first kind of VCO uses LC tank with NMOS cross-coupled pair and cross-paralleled capacitor improving the quality factor in the active port. The measured power consumption of VCO core circuit draws only 0.54mW and FOM value is 185. The second kind of VCO modfines to bulk to decreasing noise induces. That improves traditions quadrature phase VCO phase noise. The measured power consumption of VCO core circuit is 2.67mW and FOM value is 181.7 under 0.65V supply. The third kind of dual band low power QVCO simplify traditions dual band VCO circuit and adopts current-reuse topology. The measured power consumption of DB-QVCO core circuit is 5.46mW and 6.75mW under 1.3V and 1.5V supply for low band and high band. FOM value is both 171 . The second part designs low voltage PLLs that can be applied to UWB system. PLLs output frequency is 5.016GHz and including I/Q signals. The low voltage PLL adopts level shift current mode logic (LS-CML) divider at the 1st stage divider. Using reform pre-charge phase frequency detector (PFD) and refine true single phase clock (TSPC) divider. The whole loop simulated power dissipation is 5.58mW.