高介電常數材料（HfAlOxNy）在MOS元件上特性之研究

Abstract

根據半導體的微縮定律，隨著半導體製造逐漸的微小化，極薄的二氧化矽介電層將伴隨著極大的直接穿遂漏電流，而這個直接穿遂漏電流將對元件的功率消耗有嚴重的影響。在閘極二氧化矽介電層薄到10奈米以下的情況之下，為了解決這嚴重的直接穿遂漏電流現象，我們將利用高介電係數材料來替換傳統的二氧化矽。我們利用高介電係數材料在相同的等效二氧化矽厚度之下，能擁有較大的實際物理厚度以抵擋直接穿遂漏電流。

在眾多高介電係數材料之中，二氧化鉿和三氧化二铝是非常有潛力的高介電係數材料。二氧化鉿有較高的介電係數，但它的結晶溫度太低<500oC。為了克服二氧化鉿結晶溫度太低的問題，我們加入三氧化二铝去改善這問題及提升載子能障．當高介電數材料直接沈積在矽晶圓表面上時，在介面的地方會有一層二氧化矽的介面層產生．這一層介面層的品質扮演著非常重要的角色對於在元件的特性和可靠度．所以我們想要成長一層像熱二氧化矽一般，有很少的介面缺陷特性的極薄氧化層，來改介面特性和電性．在我們的實驗過程中，在成沈高介電質之前我們利用紫外光及上臭氧去成長一層高品質的極薄氧化層． 本論文首先研究以紫外加上臭氧在室溫成長的薄氧化層的基本特性．從實驗結果，我們發現利用紫外加上臭氧所成長的二氧化矽具有自我限制的飽和成長特性．接下來討論不同的沈積後退火的溫度在沈高介電質之前我們利用紫外光及上臭氧去成長一層高品質的極薄氧化層．介由電性的量得到一個適合的沈積後退火的溫度(900oC 30sec)．在第二章最後比較了有做紫外光臭氧表面、沒有做過任合表面處理及做了紫外光臭氧之後加上NH3電漿的氮化的表面處理．從漏電流密度、遲滯現象、ＴＺＢＤ、等效氧化層厚度的電性觀點來看，我們發現在沒有做過任合表面處理不管是從漏電流密度、遲滯現象、ＴＺＢＤ、等效氧化層厚度都不如有做紫外光臭氧的表面處理，而在做了紫外光臭氧之加NH3電漿的氮化的效氧化層厚度下表面處理雖然等效氧化層厚度下降，但大量的氮合併造成其它電性的衰退，像是漏電流密度、遲滯現象、ＴＺＢＤ．總合上面的結論來看，我們得到紫外光臭氧的表處理是最佳的化的條件． 在本論文的最後，利用第二章的最佳化的條件去做成nMOSFETs同時去把沒有做表面處理條件做成nMOSFETs來做比較．經由電性上的結果來看，發現有明顯的改善．最後利用CVS去探討可靠度，不管是從表面缺陷密度的增加量和Bulk的缺陷密度的增加量都也有明顯的改善．而且從結果得知不管是否有經過表面處理，都是Bulk的缺陷密度的增加量為造成臨限電壓偏移的主要原因．

According to the scaling rules, aggressive scaling has led to silicon dioxide (SiO2) gate dielectrics as ultra thin in state-of-the-art CMOS technologies. As a consequence, static leakage power due to direct tunneling through the gate oxide has been increasing at an exponential rate. As technology roadmaps call for sub-10Å gate oxides within the next five years, a variety of alternative high-k materials are being investigated as possible replacements for SiO2. The higher dielectric constants in these materials allow the use of physically thicker films, potentially reducing the tunneling current while maintaining the gate capacitance needed for scaled device operation.

Hafnium oxide ( HfO2 ) and Alumina oxide (Al2O3) are the most potential high-k material. Hafnium oxide has the higher dielectric constant, but it tends to crystallize at a relatively low process temperature (<500oC). In order to overcome this problem, add Al2O3 in HfO2 for improve crystallization temperature and barrier height. There are many interfacial states as high-k materials directly contact silicon. However, the control of SiO2-like interface between high-□ dielectrics and silicon substrate pays more and more important, since the device performances and reliability characteristics are strongly affected by the interface quality. Therefore we want to grow like thin thermal SiO2 that have very lower interface state to improve the interfacial layer and electrical characteristics. In this thesis, the basic properties of the ozone oxide were studied first. A saturated oxidation was observed in the growth curves and the resultant self-limiting property. Then different post deposition anneal is studied on HfAlOxNy gate dielectric prior UV ozone treatment. PDA can effectively improve gate dielectric quality. Therefore, post deposition anneal must to do but a suitable anneal temperature is very important on electrical characteristics. In this chapter, we find a suitable anneal temperature to improve electrical characteristics. From the hysteresis , leakage density and time zero to breakdown determine the post deposition anneal at 900 oC and that has excellent electrical characteristics. We compared with UV ozone treatment and without on electrical characteristics. We observe that, no matter on EOT, hystersis, leakage current density and TZBD have excellent electrical characteristics. By different NH3 plasma treatment’s time of UV ozone oxide prior to HfAlOxNy gate dielectric deposition were investigated. We find that NH3 nitridation would degrade device performance such hystersis, leakage current density and TZBD. Though EOT decreasing with the NH3 treatment‘s time increasing but that improvement on electrical characteristic is little. We determine the optimum condition (UV ozone surface and post deposition anneal 900oC 30s) by above result.

In the thesis final, we used optimum condition on chapter two to fabricate the nMOSFETs and a control sample (without treatment and PDA900oC 30seconds after high k film deposit) was fabricated at the same time. We can observe that improved electrical characteristics on nMOSFET with UV ozone surface treatment.Then we estimate reliability of the HfAlOxNy stacks nMOSFETs by constant voltage stress (CVS). We find that UV ozone surface treatment can improved delta interface state density and bulk charge trap density during the constant voltage stress compared with the control sample. We observe that the bulk charge density to dominate the threshold voltage shift charge during the constant voltage stress for with UV ozone treatment and without