精簡數位訊號處理器之能量效率增進

Abstract

隨著對於強大運算能力和行動力的需求持續增加，低功率和低能量消耗設計已變成超大型積體電路(VLSI)中重要的設計考量，因此近年來有許多用來改進能量或是功率的技巧被提出來，而在這些各式各樣的技巧當中，有些技巧一起使用時，有加成的效果，有些則沒有，甚至不能一起使用，因此，要達到同樣的速度需求，使用那一些技巧來達到低功率、低運算能量消耗會比較有效率，是個值得探討的問題。針對這個問題，我們提出了一個能量最佳化的設計方法，用系統化的方式，有效率地整合這些低功率、低運算能量技巧，以做出滿足速度需求且又耗能最低的設計。主要的想法在於，完成一件事所要的能量的消耗是和運算頻率沒有關係的，只和電路中電容大小、電壓高低有關係，而因為有速度的需求，電容或是電壓都有可能因此被拉高，造成更多的能量消耗，因此我們的最佳化流程，就是去用一個能量消耗的價值函數(cost function)，來評估各種增加運算速度的技巧，接著針對某一個速度需求，以這個函數去找滿足這個速度需求中，最低的能量消耗的設計方法，以這種方法去針對各個元件去做最佳化，最後再整合這些元件，來達到整體設計有最低能量的消耗。以一個用ASIC設計方式的分離餘弦轉換(discrete cosine transform)運算引擎來驗證我們的設計流程，在製程環境為TSMC 0.13 1P8M下，和傳統以速度為主要設計目標的設計方法來做比較，我們的方法能再降低4.47%的能量消耗。這個最佳化流程是針對一個固定的速度需求去做最佳化，但有時候設計會面臨到有變化的速度需求，因此我們調整這個設計流程，將一些能用來動態回收能量的技巧一併考慮進來，以滿足這種有變化的速度需求。最後，用我們所提出的最佳化方法，來對我們的目標數位訊號處理器做最佳化，和傳統的設計方式來做比較時，當速度需求在250~550MHz之間，我們的方法平均能降低8.44%的能量消耗。而我們也以這個目標數位訊號處理器去實做一個motion JPEG-based的監控系統，來說明解釋處理器所會面臨到的變化數度需求，再以我們所提的方法最佳化這個數位訊號處理器，和直接以最高速度做為最佳化目標的方式做比較，能再降低28.84%能量消耗。

There are kinds of techniques of reducing power dissipation or energy dissipation announced in recently years, some of which are additive while others may conflict. How to apply these techniques efficiently on a design is not straightforward. We proposed an energy optimization design methodology to integrate these techniques in a systematic way. The main ideal of this optimization flow is that energy dissipation is independent of the operation frequency but a constant if we consider dynamic power/energy dissipation only. Only with larger capacitance or higher supply voltage, will the energy consumption increase. The reason to use larger capacitance or higher voltage is to increase the performance of the design which is often requested in the real-time system. Our optimization flow then uses power-delay product as the cost function to meet higher performance requirement for each component. Find all cost functions from all the possible techniques that can be used to increase the performance of designs in a given design space, for examples, logic synthesis, structure, architecture and voltage. Optimize individual components via the cost functions and combine all the components to build up the entire design will result the most energy-efficient design. Use a discrete cosine transform engine build up by the ASIC approach to verify efficiency of the optimization flow we proposed with the performance requirement between 250MHz to 550MHz. With TSMC 0.13□m 1P8M CMOS cell library, our approach reduces 4.47% energy consumption in average compared with conventional design methodology which is mainly optimized for the timing constraint. The optimization flow first proposed is used to optimize the energy consumption of designs with a fixed performance requirement, while there may be varying performance requirement in real cases. The optimization flow is then modified to satisfy the varying performance requirement via using certain techniques that can be used to dynamically adjust the performance of the design. Finally, we apply the optimization flow to optimize our target DSP core. Compared the results with the conventional design methodology, our approach has 8.44% energy reduction in average. Furthermore, we use the target DSP core to construct a motion JPEG-based surveillance system to explain the varying performance requirement that processors might suffer and use the optimization flow to reduce the energy consumption for the scenario. Our approach reduces 28.84% energy dissipation of those with worst-case optimizations.