低密度對偶檢查碼解碼演算法之改進以及其高速解碼器架構之設計

Abstract

由於低密度對偶檢查碼 (LDPC) 的編碼增益接近向農 (Shannon) 極限以及解碼程序上擁有低複雜度的特性，所以在近年來受到廣泛的討論。在解碼的理論裡,尤其又以min-sum演算法最廣泛地被運用。因為想較於sum-product演算法，min-sum演算法比較適合在硬體電路的實現。本文中，我們在min-sum演算法的運算式子中加了兩個參數：固定補償參數以及動態誤差參數，相較於固定補償min-sum演算法來說，增進了解碼器的解碼效能約0.2dB。此外，在解碼器的設計上，我們使用部分平行 (partial-parallel) 的架構，此架構可同時處理兩筆不同之codewords來加快傳輸速度及資料路徑的工作效率，且共用運算單元以縮減晶片面積的大小，設計一個碼率為1/2、長度為576位元、最大循環解碼次數為10的非規則低密度對偶檢查碼解碼器，在0.18 製程下，此解碼器之資料流為每秒1.31bps、面積為95萬個邏輯閘、消耗功率為620mW。

In recent years, low-density parity-check (LDPC) codes have attracted a lot of attention due to the near Shannon limit coding gains when iteratively decoded. The min-sum decoding algorithm is extensively used because it is more suitable for VLSI implementations than sum-product algorithm. In this thesis, we propose a dynamic normalized-offset technique for min-sum algorithm and achieve a better decoding performance by about 0.2dB than normalization min-sum algorithm. Based on a partial-parallel architecture, an irregular LDPC decoder has been implemented, assuming code rate of 1/2, code length of 576 bits, and the maximum number of decoding iterations is 10. This architecture can process two different codewords concurrently to increase throughput and data path efficiency. The irregular LDPC decoder can achieve a data decoding throughput rate up to 1.31Gbps, an area of 950k gates, and a power consumption of 620mW using UMC 0.18 process technology.