考慮處理器微架構之效能最佳化布局技術

Abstract

過去的晶片布局軟體所使用的目標方程式主要著重於縮減線長與面積。由於過去晶片內部連線的延遲所需要的時間是可以忽略的，這樣的方程式被認為是足夠的。然而，隨著半導體的製程不斷進步，晶片內部連線所需要的時間如今已經不能忽略不計。這些多餘的延遲會影響到處理器的效能，但布局軟體並未考慮這些延遲。

我們提出一個方法，將微處理器架構的性能與晶片布局兩者之間的關係連結起來，以達成針對處理器效能最佳化的考慮微處理器架構的晶片布局。實驗結果顯示我們的方法的確改進性能。

In the past, floorplanner used objective functions focused on reducing wire length and area. These objective functions were considered efficient before since the latencies of interconnects were within single clock cycle or even could be neglected. However, as semiconductor technology advances, feature size continues to shrink. The communication of signals on interconnects becomes multi-cycle, therefore the latencies can not be ignored now. These latencies have impact on the performance, and most of current floorplanning frameworks do not consider these issues.

We proposed a methodology based on a heuristic for better performance in terms of microarchitecture and floorplanning achieving microarchitecture-aware floorplanning for processor performance optimization. The result from experiments shows the validity of our methodology.