以管線方法改進非同步8051處理器之效能

Abstract

8051是用途最廣的CISC處理器，因為指令長度不同，規則度也低，所以以往的實現方法都較少使用管線。管線設計的處理器，由於能夠平行處理，能夠提高整體產出。本論文之目的就是設計能在增加最少面積下，能提昇效能，以管線執行的8051處理器，稱為PA8051。 我們會將指令處理的步驟，分成Instruction Fetch (IF)，Instruction Decode (ID)，Operand Fetch (OF)，Execution(EXE)，Write Back (WB)這五個階段。管線執行的第一個重點是要能避免所有管線危障的情況，包括資料危障、結構危障、控制危障，本文中探討各種指令平行處裡可能發生的問題。第二重點在探討資料相依時，所要解決的方法。 最後的結果在行為模型下正確的通過了驗証，並以Xilinx合成器轉成電路。

8051 is the most popular CICS ISA Microprocessor, because of its different instruction length, the regulation of instruction is little. Its design is hard to implement in pipeline. The throughput of pipelined processor is higher than that of nonpipelined processor. The objective of this processor is to develop a pipelined asynchronous 8051 processor, called PA8051. We divide PA8051 into five stages, that is Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execution(EXE) and Write Back (WB). The most important problem to be resolved in pipelined design is hazard, including data hazard, structural hazard, control hazard. Thus, we analyze where the hazards happen and find the solution to solve the hazards. Finally, we successfully passed the behavior simulation and synthesized the design with Xilinx Synthesize tool.