化學機械研磨與蝕刻製程導致微影疊對誤差變異的影響研究與改善

Abstract

在IC製造過程中, 微影是最關鍵的製程之一, 直接關係著最小特徵尺寸的極限, 微影即是經由對準曝光而將光罩上電路圖案轉移至晶片上適當的位置, 層間的圖案疊合差異稱為疊對誤差, 疊對誤差過大而超過設計規範將導致元件短路或斷路,並影響產品良率, 所以疊對誤差的最小化與持續良好控制是微影最重要的課題之一.

在現今的IC製程中,微影製程不再是影響疊對誤差的唯一因素,其它製程,如化學機械研磨,蝕刻,薄膜成長等製程,也會影響微影製程的對準行為與疊對誤差結果

本論文研究主題是探討化學機械研磨與蝕刻的製程條件對微影疊對誤差造成影響的可能原因,並透過實驗驗證之,實驗結果經由固定化學機械研磨轉向與適當增加蝕刻時間,可以得到良好的疊對誤差控制.

最後我們探討了各晶圓製程可能造成的對準圖案異常,並提出微影對準科技可能改善的方向.

Lithography is the key step of IC manufacturing and directly influences the limit of critical dimension (CD).The lithography is to transfer the pattern on mask to wafer in right position, through alignment and exposure. The pattern misplacement between the layer and its previous layer is called overlay error. Once the overlay error exceeds the limit of fault tolerance defined by design rule will make circuit either open or short, and then suffers yield lost. Therefore, to minimize the overlay error and well to control the overlay error are always an important topic of lithography.

In advanced IC fabrication, lithography is no longer the only factor resulting in the misalignment. In fact, such as chemical mechanical planarization (CMP), etch, and thin film deposition also influence the alignment and overlay significantly. In this thesis, we discuss the possible factors affecting overlay error, such as chemical mechanical planarization and etching process. Finally, we demonstrate the solution by unifying CMP rotary direction and increasing over-etching to achieve tighter overlay control.

In conclusion, we discuss the wafer process that may influence alignment mark shape. Alignment improvement strategies reducing the sensitivity with wafer process is also provided.