積體電路產品之元件充電模式靜電放電測試與研究

Abstract

隨著近年來半導體積體電路製程的持續演進，元件尺寸越做越小，已朝向奈米範疇發展，並且由於積體電路運算速度的發展需求，互補式金氧半導體(CMOS)製程技術持續進展，並降低電晶體的閘極氧化層厚度，以提升電路工作頻率；但對靜電放電(Electrostatic Discharge, ESD)而言，較薄的閘極氧化層厚度，意味著電晶體閘極更容易遭受靜電放電轟擊而毀損。在先進互補式金氧半(CMOS)製程中，這種電晶體閘極毀損的情況，在晶片層級元件充電模式(Chip-Level Charged-Device-Model, CDM)靜電放電測試時極為明顯。然而在電子產品應用中，當晶片黏貼至電路板上時，若電路板本身因為摩擦或感應而累積電荷，電路板上累積的電荷，會經由電荷重新分配的過程傳遞至晶片中，並瞬間產生非常大的電流流入晶片，造成晶片損壞，此為電路板層級元件充電模式(Board-Level CDM)靜電放電的成因。 本篇論文的第一部份在探討電路板層級(Board-Level)及晶片層級元件充電模式(Chip-Level CDM)靜電放電在積體電路產品上的行為特性研究與所造成的威脅，且針對實際實驗案例，以故障分析(Failure Analysis)的手法，進行對遭受晶片層級元件充電模式靜電放電測試損害之元件作故障定位(Fault Isolation)，並找出元件充電模式靜電放電所造成之故障機制(Failure Mechanism)比較及探討。 本篇論文的第二部份是以實驗模擬的方式，對數個以互補式金氧半製程製作的測試元件與測試電路進行電路板層級與晶片層級元件充電模式靜電放電測試，首先由於電路板層級元件充電模式靜電放電的電流峰值與電子模組中的電路板尺寸有密切的關係，故針對不同電路板尺寸所產生的電路板層級元件充電模式靜電放電波形進行量測，實驗結果顯示較大的電路板尺寸或將電路板充電至較高電壓，將導致較大的電路板層級元件充電模式靜電放電電流峰值；其次針對測試元件與測試電路進行電路板層級與晶片層級元件充電模式靜電放電測試，測試結果發現電路板層級元件充電模式靜電放電耐受度較低，且證實電路板層級元件充電模式對積體電路產品所造成的損害，遠比晶片層級元件充電模式來的嚴重。 本論文透過實驗的結果，成功證明電路板層級元件充電模式靜電放電在積體電路產品所造成的損害，遠比晶片層級元件充電模式來的嚴重，而且常容易被誤認為過度電性應力(Electrical Over Stress, EOS)，由於目前對電路板層級的靜電放電測試尚未有明確規範，經由本論文實驗步驟的建立，可供日後規範建立的參考。

With the continuous evolution of semiconductor integrated circuit (IC) process, the device dimension growing narrow down and developing into nanoscale. Moreover, the transistors have been fabricated with thinner gate oxides to achieve higher speed or operation frequency due to the operation speed requirement of integrated circuits (ICs) in advanced process of complementary metal-oxide semiconductor (CMOS). In electrostatic discharge (ESD) events, the transistors are more easily damaged during ESD stress if they are fabricated with thinner gate oxides. The situation of gate oxide damage of transistors is a typical and familiar failure mechanism during chip-level charged-device-model (CDM) ESD test, especially in CMOS process. But in the applications of microelectronic system, IC chips must to be attached to the printed circuit board (PCB). The static charges will be stored in the PCB due to induction or rub and then deliver the charges to the IC chips through redistribution process during the attachment of IC chips to PCB. The instantaneous current flows into the IC chips is huge and will result in the damage of IC chips. It is the cause of board-level CDM ESD event. In the first part of this thesis, the focus is the investigation of characteristics and threats on board-level and chip-level CDM ESD in IC products. Furthermore, from the experimental results, the technique of failure analysis (FA) with fault isolation is applied to summarize the comparison of CDM failure mechanism caused by ESD event during CDM ESD test. The second part presents an experiment of ESD test between board-level and chip-level CDM on several samples fabricated with CMOS process. At first, the board-level CDM ESD current waveforms under different sizes of printed circuit boards (PCBs) and different charged voltage are measured. The experiment result has shown that the discharging current strongly depends on the PCB size and the charged voltage. Moreover, chip-level and board-level CDM ESD levels of several test devices and test circuits have been characterized and compared. Test results have shown that the board-level CDM ESD level of the test circuit is lower than the chip-level CDM ESD level, which demonstrates that the board-level CDM ESD event is more critical than the chip-level CDM ESD event. In addition, failure analysis reveals that the failure on the test circuit under the board-level CDM ESD test is much severer than that under the chip-level CDM ESD test. Based on the experiment results in this thesis, it is successfully proved that the failures caused by board-level CDM ESD event are more server than chip-level CDM ESD event and are easily mistaken for electrical over stress (EOS) related failures. Since the standard for the board-level CDM ESD test is not established so far, the experiment procedures in this thesis can be the reference for the establishment of the board-level CDM ESD test standard.