非同步AVR微控器設計及實現

Abstract

非同步電路有諸多的優點，例如時脈歪斜問題的消除、平均效能的表現、以及低功率消耗的特性，在在吸引著我們去深入探討這樣特性的電路結構。尤其是低消耗功率的特性 , 對於現今行動裝置產品而言是非常重要的。 本篇論文針對ATMEL公司8 位元RISC架構的AVR微控制器，以非同步電路的方式將其重新設計與做部分的實現。 我們採用 Sutherland 的微管線（Micropipeline）架構做為設計基礎，修改成為雙軌（dual rail）與延遲無關（delay insensitive）的電路設計，將整個非同步處理器設計結合目前的同步電路工具進行合成 , 並將設計下載至 FPGA 晶片以完成實現。 我們完成了算術及邏輯運算指令如ADD、SUB、AND、OR，資料搬移指令如MOV、LSI，分支指令如JMP等主要的指令，以建構成我們的非同步版本的 AVR 微控制器。

There are many advantages which allure us to explore contents of asynchronous circuits on asynchronous circuits, such as elimination of clock skew problems, average case performance and lower system power consumption. Furthermore, low power consumption is one of the most important issues for mobile devices. This thesis focus on the implementation of an asynchronous Atmel AVR 8-bit RISC microcontroller. We implement our design with Sutherland’s dual rail DI micropipeline. The whole asynchronous AVR microcontroller was synthesized with current synchronous EDA tools, and realized with FPGA chip. The following instructions were accomplished: arithmetic and logic instructions, such as ADD, SUB, AND, OR; data transfer instructions, such as MOV, LDI; branch instructions, such as JMP. These instructions were used to comprise our asynchronous AVR microcontroller.