全數位控制寬頻振盪器之研究

Abstract

這個論文研究全數位鎖相回路振盪器之研究.。如何增加頻寬,，增高解析度和降低抖動的影嚮是我們全篇論文的重點。我們的設計是一個寬頻的輸出，我們可以輸出的頻率從0.66~460 MHz，每一步可以改變2.16奈秒。這個設計是一個數位訊號轉換為時間的設計，我們用數位訊號改變輸出的頻寬。我們在這裡也用到 AOI 和 OAI 作為微調的元件，這個元件可以提供0.01皮秒(pico-seconds)的解析度。為了降低抖動，我們使用電流鏡來達成我們的目的。如同眾所周知的，電感、電阻和電容的效應將使瞬間的電流破壞電壓源的穩定度，也將使得輸出的訊號不停的抖動。電流鏡可以使我們的設計穩定電壓源，也使得輸出的訊號更好。我們這篇論文的重點就會在寬頻、高解析度及降低抖動上面。從一些模擬的實驗上就可以看出我們設計的效果。我們更將把這個設計做到晶片上面，從實際的晶片來驗證我們設計的效果。

The thesis is based on All-digital-Phase-Locked- Loops (ADPLL).. We will discuss wide band, cell-based digital controlled oscillator (DCO) in this thesis. In our design, there is a wide bandwidth DCO. The frequency is from 0.66~ 460MHz step by 2.16ns. It is designed by Digital-to-Time (DTC) scheme. We also use AOI and OAI as Fine-tune cells. The best resolution of this design is 0.01 pico-seconds. We use UMC 90nm standard cell AOI to get this performance. In another way, we put current mirror in DCO for reduction of bounce noise. That will effectively reduce jitter caused by ground bounce. The wide bandwidth DCO use DTC to do the internal count for different bandwidth. That is a double loops scheme. AOI cell is the standard cell for fine tune solution. When we change the control bits of AOI, it change the capacitance of additional capacitor. The resolution of 0.01 pico-seconds is a good performance for DCO design. The output jitter is another issue. When the design is working, the transient current will make a serious ground bounce. It is the major source of jitter. How to reduce the ground bounce and jitter is the important topic for DCO design. Here we use current mirror to reduce the ground bounce and make the clean signal.