具有寫入輔助電路的穩健低功率靜態隨機存取記憶體

Abstract

本論文提出一個具有寫入輔助電路的靜態隨機存取記憶體。此寫入輔助電路可用來解決而嚴重的Write Half-Select 的寫入問題，而且經過模擬的結果指出，此類型的寫入輔助電路在65nm 和45nm 之類的先進製程下，仍然可以維持作用良好的情況。除此之外，更額外設計了讀取與寫入的複製電路用來控制精準的時序。根據模擬結果指出，這個靜態隨機存取記憶體大量的降低了功率的消耗便且擁有非常大的電壓操作範圍，它可在電壓為1V 時，操作頻率高達1GHz，而電壓為0.5V 時，操作頻率則可達200MHz，所消耗的功率分別為9mW 與826uW，極有利於行動裝置的使用。

This paper presents a floating BL 8T SRAM Read/Write scheme. A Write assist scheme is also proposed to resolve the serious Write half-select disturb problem, and simulation results show that the proposed Write scheme can work well in more advanced technology nodes, such as 65nm and 45nm. Furthermore, Read/Write replica circuits are designed to control access timing. Moreover, a 32-Kb 8T SRAM subarray is implemented in UMC 90nm CMOS technology. According to simulation results, the proposed 8T SRAM shows its benefits on low power access operations and wide-operating voltage range. It can operate at 1GHz when VDD is 1V and at 200MHz when VDD is 0.5V. So it is suitable to be adopted in portable devices.