連續時間和差類比數位轉換器之迴圈延遲補償器設計之研究

Abstract

和差調變器以往是非常廣泛的應用於低中頻寬、高解析度的一項技術。然而相較於過去傳統所常用的交換型電容(離散時間)的技術，隨著對於頻寬需求的增加，連續型的電路設計方式將會更適合於現今高頻寬的應用。本論文就實現連續型和差調變器來做一些探討。在於和差調變器回授路徑上，不同的延遲時間將會依據一些數學理論來做詳細地分析。此晶片使用台積電0.18μm CMOS 製程，供應電壓為1.8 V，消耗功率為6.5-mW，晶片核心面積為0.05mm2。模擬結果在100MHz的取樣頻率、2MHz 的頻寬內得到峰值SNDR為 62dB。

A ΔΣ modulator is well-known as a very efficient technique for the implementation of high resolution A/D converters in low to medium bandwidth applications. Comparing with switched-capacitor (discrete-time) technique in the past, the continuous time circuitry is more suitable for today’s growing bandwidth applications. The thesis presents the implementation of a ΔΣ modulator with continuous-time techniques. Different numbers of digital delay in the ΔΣ feedback loop have been analyzed based on mathematic theorems in detail. The chip is designed with 1.8V power supply by using 0.18μm TSMC CMOS process, with power consumption 6.5mW and the core area 0.05mm2. The simulation result shows that the ADC achieves a 62dB peak signal-to-noise pulse distortion ratio (Peak-SNDR) within a 2MHz bandwidth with a sampling rate of 100MHz