降低晶片上匯流排雜訊之匯流排編碼技術之研究

Abstract

隨著製程演進至奈米科技，長導線之電路延遲與功率消耗，已經成為晶片設計上之棘手難題，此外，導線間，電感與電容偶合效應，也在電路上造成極嚴重問題，如串音，雜訊造成的電路延遲與多餘功率消耗等，因此，在現今高速晶片匯流排之設計上，設計者必須面對比以往更加嚴重的偶合效應所造成之電路延遲與功率消耗。 現今已經發表之晶片上匯流排編碼技術，大部分單純考慮電容偶合效應(造成最長延遲之匯流排輸入組態為由電容偶合效應所造成)從而導出其編碼系統，因此，這些編碼技術有可能無法適用於超深次微米製程下之電路，尤其是在電感偶合效應非常明顯之狀況。 在本篇論文中，我們首先透過一系列實驗，呈現出在只考慮電容與同時考慮電感電容偶合效應下，所得到之最差輸入轉變組態，並發覺這兩種不同考量下所得到之結果極為不同，從而證實，前人所提出的編碼技術，由於單純考慮電容偶合效應，所以應用於電感偶合效應強烈的電路設計時，可能無法改善匯流排電路延遲，甚或造成額外的電路延遲。 在發現此一現象後，針對強烈電感偶合效應做造成之匯流排延遲，我們提出以bus-invert方法來降低電路延遲，根據我們實驗結果，此一方法確實可有效降低電感偶合所造成之匯流排電路延遲。 接著，根據模擬結果，在同時考量導線電容與電感效應下，我們發現匯流排之最差輸入組態，會依據電路設計者所使用之參數，而有所不同，然而bus-invert方法只適用於降低電感效應為主之雜訊，應用上會有所限制，所以為了改善bus-invert使用上的限制，我們另外提出一種有彈性之匯流排編碼技術，此種編碼技術會依據設計者輸入之設計參數，產生出不同之編碼結果，以符合使用者需求，此外，經過適當修改，依據所給定之限制，此一編碼系統可應用於預測與增長訊號傳輸距離，接著我們也以實驗結果來支持我們的論點。 接下來，為了可更有效地降低導線偶合雜訊與改善我們編碼系統之效能，我們提出一個同時利用編碼與插地線之技術，以適用於未來奈米製程下之匯流排設計，此一技術可依據使用者所給定之匯流排參數、工作頻率與限制，產生一組可有效降低電容電感耦合效應之匯流排編碼與架構，從而降低電路延遲，實驗結果也證實，此項技術確實可有效降低電路延遲。 由於導線之功率消耗業已成為現今高效能電路設計之棘手難題，有鑑於此，在考量使用者給定之延遲限制下，我們首先提出利用有彈性之匯流排編碼技術，以降低匯流排功率消耗；為得到更好的改善效果，接著我們也提出一個同時利用編碼與插地線之技術，在給定匯流排參數、工作頻率與延遲限制下，用以降低匯流排功率消耗，模擬結果證實，此兩項技術確實可在考量各種參數與延遲限制下，產生可達成匯流排功率消耗極小化之匯流排編碼，除此之外，比較有彈性之匯流排編碼技術，同時利用編碼與插地線之技術也確實能得到更好之匯流排功率改善效果。

As technology advances, the global interconnect delay and the power consumption of long wires become crucial issues in nanometer technologies. In particular, both inductive and capacitive coupling effects between wires result in serious problems such as crosstalk delay, coupling noise, and power consumption. Hence, the strong coupling effects between wires make the delay and power consumption of on-chip buses worse than before. Therefore, it is crucial to reduce the delay and power consumption of the on-chip bus to improve the circuit performance in DSM designs. Most existing works consider only RC effects (the worst-case switching pattern resulting from coupling capacitance) to develop their encoding schemes to reduce the bus delay and/or the bus power consumption. Therefore, their works may not be suitable for the very deep-submicron designs when the inductive coupling becomes significant. In this dissertation, we first show that the worst-case switching pattern that incurs the longest bus delay while considering the RLC effect is quite different from that while considering RC effect alone. It implies that the existing encoding schemes based on the RC model may not improve or possibly worsen the delay when the inductance effects become dominant. Then we propose a bus-invert method to reduce the worst-case on-chip bus delay with the dominance of the inductance coupling effect. Simulation results have shown that our encoding method can significantly reduce the worst coupling delay of the buses with strong inductive coupling. From our simulation results, we observe that the worst-case switching pattern could vary with given design parameters considering the RLC effects of interconnects. However, the proposed bus-invert method can be utilized to reduce the bus coupling delay only when the inductance effects dominate. Therefore, we propose a flexible encoding scheme for on-chip buses that can consider the given parameters to reduce the LC coupling delay. In addition, with some modification, this new encoding scheme can be utilized to predict and lengthen the signal propagation length of a bus under the given constraints. Simulation results are also given to support our claims. Next, to further reduce the coupling noise, we propose a joint shield insertion and bus encoding scheme for global bus design in nanometer technologies. With the user-given bus parameters, the working frequency, the scheme can effectively reduce the LC coupling effects and hence, minimize the bus coupling delay. Simulation results show that the proposed scheme can significantly reduce the coupling delay. Recently, the power consumption of on-chip interconnect is another crucial issue in high performance circuit designs. First, we propose a flexible encoding scheme to minimize the power consumption of buses under given delay constraints. To further improve the performance of the encoding scheme (further reduce the power consumption), we also utilize the joint shield insertion and bus encoding method to solve the problem. With the user-given bus parameters, the working frequency, and the delay constraint, both schemes can minimize the bus power consumption subject to the delay constraint by effectively reducing the LC coupling effects. Simulation results show that the proposed schemes can significantly reduce the coupling delay and the power consumption of a bus according to the delay constraint. In addition, the joint shield insertion and bus encoding method can gain more power reduction than that gained by only using the flexible bus encoding scheme.