應用於10GBASE-LX4之3.125GHz半速率時脈資料回復電路

Abstract

本論文利用TSMC 0.18um製程實現一運用在10GBASE-LX4乙太網路中的3.125GHz時脈資料回復電路。所使用的架構為半速率相位鎖定式時脈資料回復電路，電路中包含相位檢測器、充電泵、迴路濾波器、壓控振盪器四個部份，其中低通迴路濾波器為外掛，其餘皆以IC方式實現。相位檢測器為半速率線性相位檢測器，降低電路操作的頻率以減少功率的消耗。壓控振盪器為二級環形壓控振盪器，有較大的可調頻率範圍及減少振盪器的功率消耗，並得到兩正交輸出。先利用Matlab作行為模式模擬，再利用HSPICE作整體電路的閉迴路模擬，整體電路在1.8V供應電壓下，核心電路消耗功率17.77mW，若包含Buffer則為45.57mW。

The purpose of this paper is to implement a 3.125GHZ clock and data recovery circuit (CDR) for 10GBASE-LX4 by using TSMC 0.18um process. The structure of the CDR belongs to the phase locked loop. It consists of phase detector, charge pump, loop filter, and VCO. The loop filter is off chip. The half-rate linear phase detector. is employed to reduce the operating frequency and power consumptions. Two-stage ring oscillator is used as VCO to achieve wide tuning range and the low power consumption of the VCO. After the behavior model simulate with Matlab, the close loop behavior of over all circuit is verified with HSPICE. Under 1.8V supply voltage, the power consumption of the core circuit is 17.77mW. The power consumption of the over all circuit including the buffer is 45.57mW.