不同高介電常數與傳統低溫介電層應用於低溫複晶矽薄膜電晶體之比較

Abstract

摘要 (中文) 本論文中,擁有高效能P型通道薄膜電晶體以不同的高介電係數介電層材料(包括二氧化鉿（HfO2）、鉿矽酸鹽（Hf-silicate）被提出,以金屬-有機汽相沉積的高介電係數介電層與傳統二氧化矽(TEOS-Oxide)介電層在低溫環境中被製作出來,以相同物理厚度比較作為我們的主軸,並且研究其效應與可靠度。我們發現高介電常數在電性的表現上有著普遍性的增長：包括了較低的臨界電壓、較好的次臨界特性、較高的驅動電流；最主要原因在於高介電常數介電層有較高的電容密度,使得多晶矽結晶邊界的載子缺陷能快速被填滿,因而多晶矽電晶體存在的暫態時間較為縮短。然而二氧化鉿介電層的場效遷移率卻是較低的，並且在關閉狀態下的漏電流增加較快，原因在於其跟複晶矽通道間的介面特性較為曲折,以及由於高介電常數所造成的在汲極端有較大的電場有關。 不同介電層的複晶矽薄膜電晶體，在不同溫度的加壓測試下都會隨著測試時間的改變而裂化,其中鉿矽酸鹽在目前的測試中展現了較佳的可靠度,主要在於其有較高的結晶溫度、較好的薄膜品質與較少的介面狀態密度。

Abstract (English)

In thesis, high-performance p-channel poly-Si thin-film transisitors (TFTs) are demonstrated using the different high-k dielectric with hafnium dioxide (HfO2), hafnium silicate (HfSiOX) layer are demonstrated by metal-organic chemical vapor deposition system with low-temperature processing. We compare with tetra-ethyl-oxy-silicate silicon dioxide (TEOS-SiO2) layer with the same physics thickness for our main shaft. Furthermore, the effect and reliability are also studied. It is found both the electric characteristic of high-k dielectric TFTs that improve obviously: including the lower threshold voltage, the better subthreshold swing, the higher on current. The main reason is imputed to the high capacitance density of high-k dielectric layers such that the grain boundary traps of poly-Si could be full faster and decrease the transition time exist in the poly-Si TFTs. However, the field effective mobility of HfO2 dielectric TFTs is lower due to the roughness interface between HfO2 layer and poly-Si channel and larger leakage current in the off state due to the high field near drain. Devices characteristics of different dielectric layers degrade with stress time and stress conditions. We found the HfSiO dielectrics TFTs have the better reliability due to it has the better interface ,higher crystalline temperature and lower density of states.