完整後設資料紀錄
DC 欄位語言
dc.contributor.authorKuo, Chien-Ien_US
dc.contributor.authorHsu, Hen-Tungen_US
dc.contributor.authorChang, Edward Yien_US
dc.contributor.authorMiyamoto, Yasuyukien_US
dc.contributor.authorTsern, Wen-Chungen_US
dc.date.accessioned2014-12-08T15:10:58Z-
dc.date.available2014-12-08T15:10:58Z-
dc.date.issued2008-09-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.47.7119en_US
dc.identifier.urihttp://hdl.handle.net/11536/8397-
dc.description.abstractAn InAs/In(0.3)As composite channel high-electron-mobility transistor (HEMT) fabricated using the gate sinking technique was realized for ultralow-power-consumption low-noise application. The device has a very high transconductance of 100 mS/mm at at drain voltage of 0.5 V. The saturated drain-Source current of the device is 1066 mA/mm. A current grin cutoff frequency (f(T)) of 113 GHz and a maximum oscillation frequency (f(max)) of 110GHz were achieved at only drain bias volume V(ds) = 0.1V. The 0.08 x 40 mu m(2) device demonstrated a minimum noise figure of 0.82 dB and a 14 dB associated gain at 17GHz with 1.14mW DC power consumption.en_US
dc.language.isoen_USen_US
dc.subjectInAs/InGaAsen_US
dc.subjectgate sinkingen_US
dc.subjectcurrent gain cutoff frequency (f(T))en_US
dc.subjectultralow poweren_US
dc.titleInAs high electron mobility transistors with buried gate for ultralow-power-consumption low-noise amplifier applicationen_US
dc.typeArticleen_US
dc.identifier.doi10.1143/JJAP.47.7119en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume47en_US
dc.citation.issue9en_US
dc.citation.spage7119en_US
dc.citation.epage7121en_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.identifier.wosnumberWOS:000259657700023-
dc.citation.woscount10-
顯示於類別:期刊論文


文件中的檔案:

  1. 000259657700023.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。