Design and implementation of a high-performance and complexity-effective VLIW DSP for multimedia applications

Abstract

This paper presents the design and implementation of a novel VLIW digital signal processor (DSP) for multimedia applications. The DSP core embodies a distributed & ping-pong register file, which saves 76.8% silicon area and improves 46.9% access time of centralized ones found in most VLIW processors by restricting its access patterns. However, it still has comparable performance (estimated in cycles) with state-of-the-art DSP for multimedia applications. A hierarchical instruction encoding scheme is also adopted to reduce the program sizes to 24.1 similar to 26.0%. The DSP has been fabricated in the UMC 0.13 mu m 1P8M Copper Logic Process, and it can operate at 333 MHz while consuming 189 mW power. The core size is 3.2 x 3.15 mm(2) including 160 KB on-chip SRAM.