高介電閘氧化層深次微米MOS元件電漿製程傷害可靠性之研究

標題:	高介電閘氧化層深次微米MOS元件電漿製程傷害可靠性之研究 Study of the Plasma Induced Reliabilities in High-K Gate Dielectric Submicron MOSFETs
作者:	莊紹勳 Chung Steve S 國立交通大學電子工程學系
關鍵字:	高介電閘;介電層;電漿製程;可靠性;金氧半場效電晶體;High dielectric gate;Dielectric layer;Plasma process;Reliability;MOSFET
公開日期:	2001
官方說明文件#:	NSC90-2215-E009-065
URI:	http://hdl.handle.net/11536/96596 https://www.grb.gov.tw/search/planDetail?id=665692&docId=126371
Appears in Collections:	Research Plans

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