運用時域方法之10G/s 可適性纜線等化器設計(II)

Abstract

本計畫將針對10Gb/s 銅線通訊系統應用，以標準CMOS 製程技術開發其接收 端之自適性等化器。傳統之頻域分析與設計方式，因其功率偵測器之轉換增益過低， 故其等化器之工作狀態極易受製程、電壓、溫度等變異之影響。有鑑於此，本計畫 將運用如斜率偵測、過激偵測、相位偵測等時域技術來提升可靠度，並發展可以快 速鎖定之低功耗架構，以期實現具高可靠度、高增益補償範圍、低功耗、以及快速 鎖定性能之最佳化設計。對於超高速之應用，雙二位元接收等化器可有效降低對通 道頻寬之要求，然而目前並無適當之自動補償控制機制，因而相關技術之開發亦是 本計畫之重點工作之ㄧ。

The goal of this project is to develop the adaptive equalizer in the receiver front-end for 10Gb/s cable communication applications using standard CMOS technology. Conventional frequency-domain approaches are used to build adaptive equalizers. However, the resulting small conversion gain of the power detector makes the operation of the adaptive equalizer quite sensitive to those undesired PVT variations. In this project, the time-domain techniques, such as the slope detection, overshot detection and phase detection, will be utilized to improve the reliability. Combined with our low-power and fast-locking design topology, a reliable low-power fast-locking adaptive equalizer with a wide gain tuning range can be achieved by the end of this project. For ultra-high speed applications, duobinary receiving equalizers have attracted many interests due to the corresponding relaxed requirement in channel bandwidth. However, the lack of a simple adaptive compensation mechanism becomes a major issue. It is also part of the objective of this project to develop a robust design architecture for adaptive duobinary equalizers.