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公開日期標題作者
九月-2016A Film-Profile-Engineered 3-D InGaZnO Inverter Technology With Systematically Tunable Threshold VoltageLyu, Rong-Jhe; Lin, Horng-Chih; Li, Pei-Wen; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016Film-Profile-Engineered IGZO Thin-Film Transistors with Gate/Drain Offset for High Voltage OperationWu, Ming-Hung; Lin, Horng-Chih; Li, Pei-Wen; Huang, Tiao-Yuan; 電機學院; 電子工程學系及電子研究所; College of Electrical and Computer Engineering; Department of Electronics Engineering and Institute of Electronics
1-四月-2014Gate-all-around floating-gate memory device with triangular poly-Si nanowire channelsTsai, Jung-Ruey; Lee, Ko-Hui; Lin, Horng-Chih; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016High-gain, Low-voltage BEOL Logic Gate Inverter Built with Film Profile Engineered IGZO TransistorsLyu, Rong-Jhe; Chiu, Yun-Hsuan; Lin, Horng-Chih; Li, Pei-Wen; Huang, Tiao-Yuan; 電機學院; 電子工程學系及電子研究所; College of Electrical and Computer Engineering; Department of Electronics Engineering and Institute of Electronics
1-十月-2007High-performance and low-temperature-compatible p-channel polycrystalline-silicon TFTs using hafnium-silicate gate dielectricYang, Ming-Jui; Chien, Chao-Hsin; Lu, Yi-Hsien; Luo, Guang-Li; Chiu, Su-Ching; Lou, Chun-Che; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
三月-2016High-Performance Submicrometer ZnON Thin-Film Transistors With Record Field-Effect MobilityKuan, Chin-I; Lin, Horng-Chih; Li, Pei-Wen; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2016Impact of gate dielectrics and oxygen annealing on tin-oxide thin-film transistorsZhong, Chia-Wen; Lin, Horng-Chih; Tsai, Jung-Ruey; Liu, Kou-Chen; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
四月-2016Impact of gate dielectrics and oxygen annealing on tin-oxide thin-film transistorsZhong, Chia-Wen; Lin, Horng-Chih; Tsai, Jung-Ruey; Liu, Kou-Chen; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2015Impact of Residual Hardmask Wires on the Performance of Film-Profile-Engineered ZnO Thin-Film Transistors With Discrete Bottom GatesLyu, Rong-Jhe; Lin, Horng-Chih; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
一月-2016Impact of thermal oxygen annealing on the properties of tin oxide films and characteristics of p-type thin-film transistorsZhong, Chia-Wen; Lin, Horng-Chih; Liu, Kou-Chen; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2016Impact of thermal oxygen annealing on the properties of tin oxide films and characteristics of p-type thin-film transistorsZhong, Chia-Wen; Lin, Horng-Chih; Liu, Kou-Chen; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Impacts of a buffer layer and hi-wafers on the performance of strained-channel NMOSFETs with SiN capping layerTsai, Tzu-, I; Lee, Yao-Jen; Chen, King-Sheng; Wang, Jeff; Wan, Chia-Chen; Hsueh, Fu-Kuo; Lin, Horng-Chih; Chao, Tien-Sheng; Huang, Tiao-Yuan; 物理研究所; 電子工程學系及電子研究所; Institute of Physics; Department of Electronics Engineering and Institute of Electronics
1-十月-2008Impacts of a buffer layer and hydrogen-annealed wafers on the performance of strained-channel nMOSFETs with SiN-capping layerTsai, Tzu-I; Lin, Horng-Chih; Lee, Yao-Jen; Chen, King-Sheng; Wang, Jeff; Hsueh, Fu-Kuo; Chao, Tien-Sheng; Huang, Tiao-Yuan; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-四月-2007Impacts of low-pressure chemical vapor deposition-SiN capping layer and lateral distribution of interface traps on hot-carrier stress of n-channel metal-oxide-semiconductor field-effect-transistorsLu, Ching-Sen; Lin, Horng-Chih; Huang, Jian-Ming; Lu, Chia-Yu; Lee, Yao-Jen; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2011Impacts of Multiple-Gated Configuration on the Characteristics of Poly-Si Nanowire SONOS DevicesHsu, Hsing-Hui; Lin, Horng-Chih; Luo, Cheng-Wei; Su, Chun-Jung; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2011Impacts of Nanocrystal Location on the Operation of Trap-Layer-Engineered Poly-Si Nanowired Gate-All-Around SONOS Memory DevicesLuo, Cheng-Wei; Lin, Horng-Chih; Lee, Ko-Hui; Chen, Wei-Chen; Hsu, Hsing-Hui; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Impacts of precursor flow rate and temperature of PECVD-SiN capping films on strained-channel NMOSFETsLu, Ching-Sen; Lin, Horng-Chih; Lee, Yao-Jen; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十月-2008Impacts of SiN deposition parameters on n-channel metal-oxide-semiconductor field-effect-transistorsLu, Ching-Sen; Lin, Horng-Chih; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-2014Implementation of Film Profile Engineering in the Fabrication of ZnO Thin-Film TransistorsLyu, Rong-Jhe; Lin, Horng-Chih; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Improved hot carrier reliability in strained-channel NMOSFETS with TEOS buffer layerLu, Ching-Sen; Lin, Horng-Chih; Lee, Yao-Jen; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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