瀏覽 的方式: 關鍵字 guard ring

跳到: 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
或是輸入前幾個字:  
顯示 1 到 8 筆資料,總共 8 筆
公開日期標題作者
1-十二月-2014Active Guard Ring to Improve Latch-Up ImmunityTsai, Hui-Wen; Ker, Ming-Dou; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015Compensation Circuit with Additional Junction Sensor to Enhance Latchup Immunity for CMOS Integrated CircuitsTsai, Hui-Wen; Ker, Ming-Dou; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Investigation on Latch-Up Path between I/O PMOS and Core PMOS in a 0.18-mu m CMOS ProcessChen, Chun-Cheng; Ker, Ming-Dou; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jun-2015Latch-Up Protection Design With Corresponding Complementary Current to Suppress the Effect of External Current TriggersTsai, Hui-Wen; Ker, Ming-Dou; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-May-2003Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technologyKer, MD; Lo, WY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Apr-2019Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated CircuitsChen, Chun-Cheng; Ker, Ming-Dou; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015提升積體電路栓鎖防疫能力之設計方法與實現蔡惠雯; Tsai, Hui-Wen; 柯明道; Ker, Ming-Dou; 電子工程學系 電子研究所
2006針對Giga-Hertz基底雜訊抑制的主動保護電路王建龍; 李育民; 溫瓌岸; 電信工程研究所