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公開日期標題作者
1-五月-2000A 256 mA 0.72 V ground bounce output driverYu, PC; Chang, HH; Wu, JC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十月-1998A 723-MHz 17.2-mW CMOS programmable counterChang, HH; Wu, JC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十月-1998A 723-MHz 17.2-mW CMOS programmable counterChang, HH; Wu, JC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-1996Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASICKer, MD; Wu, CY; Cheng, T; Chang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-1996Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASICKer, MD; Wu, CY; Cheng, T; Chang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2000Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup dangerKer, MD; Chang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-1996Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSIKer, MD; Wu, CY; Chang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2000Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applicationsKer, MD; Chen, TY; Wu, CY; Chang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-1999Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technologyChang, HH; Ker, MD; Wu, JC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1995Efficient layout style of cmos output buffer to improve driving capability of low-voltage submicron cmos IC'sKer, MD; Wu, CY; Cheng, T; Chang, HH; Wu, MJN; Yu, TL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2000ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applicationsKer, MD; Chen, TY; Wu, CY; Chang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-1997A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC'sKer, MD; Chang, HH; Wu, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-1998Improved output ESD protection by dynamic gate floating designChang, HH; Ker, MD; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2000New diode string design with very low leakage current for using in power supply ESD clamp circuitsKer, MD; Lo, WY; Chang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-1999New layout design for submicron CMOS output transistors to improve driving capability and ESD robustnessKer, MD; Chen, TY; Chang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2000Optimization of parameter design: an intelligent approach using neural network and simulated annealingSu, CT; Chang, HH; 工業工程與管理學系; Department of Industrial Engineering and Management
1-九月-2000Parameter design optimization via neural network and genetic algorithmSu, CT; Chiu, CC; Chang, HH; 工業工程與管理學系; Department of Industrial Engineering and Management
1-十二月-2005Topology-aided cross-layer fast handoff designs for IEEE 802.11/Mobile IP environmentsTseng, CC; Yen, LH; Chang, HH; Hsu, KC; 交大名義發表; National Chiao Tung University
顯示 1 到 18 筆資料，總共 18 筆