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公開日期標題作者
2005Adaptive encoding scheme for test volume/time reduction in SoC scan testingLin, SP; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2002Analysis of application of the IDDQ technique to the deep sub-micron VLSI testingLu, CW; Lee, CL; Su, CC; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-2000A behavior-level fault model for the closed-loop operational amplifierChang, YJ; Lee, CL; Chen, JE; Su, CC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
18-七月-2002BIST scheme for DAC testingChang, SJ; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2005A cocktail approach on random access scan toward low power and high efficiency testLin, SP; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-1999A compiled-code parallel pattern logic simulator with inertial delay modelHuang, KC; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002An efficient test and diagnosis scheme for the feedback type of analog circuits with minimal added circuitsLin, JW; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1995Factorization of multi-valued logic functionsWang, HM; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1996A fast and sensitive built-in current sensor for IDDQ testingLu, CW; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001Fault diagnosis for linear analog circuitsLin, JW; Lee, CL; Su, CC; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2000Fault diagnosis for linear analog circuitsLin, JW; Lee, CL; Su, CC; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1997Fault diagnosis of odd-even sorting networksHu, CW; Lee, CL; Wu, WC; Chen, JE; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
2005Finite state machine synthesis for at-speed oscillation testabilityLi, KSM; Lee, CL; Jiang, T; Su, CC; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1997Functional test pattern generation for CMOS operational amplifierChang, SJ; Lee, CL; Chen, JE; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-九月-1997Identification of robust untestable path delay faultsWu, WC; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-1997Identifying invalid states for sequential circuit test generationLiang, HC; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-1997Identifying invalid states for sequential circuit test generationLiang, HC; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1996Invalid state identification for sequential circuit test generationLiang, HC; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1998Maximization of power dissipation under random excitation for burn-in testingHuang, KC; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2000A methodology for fault model development for hierarchical linear systemsHuang, YC; Lee, CL; Lin, JW; Chen, JE; Su, CC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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