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公開日期標題作者
2015ESD Protection Design with Latchup-Free Immunity in 120V SOI ProcessHuang, Yi-Jie; Ker, Ming-Dou; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2006Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS processHsu, Sheng-Fu; Ker, Ming-Dou; Lin, Geeng-Lih; Jou, Yeh-Ning; 電機學院; College of Electrical and Computer Engineering
2015Impact of Guard Ring Layout on the Stacked Low-Voltage PMOS for High-Voltage ESD ProtectionLiao, Seian-Feng; Tang, Kai-Neng; Ker, Ming-Dou; Yeh, Jia-Rong; Chiou, Hwa-Chyi; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007The impact of high-voltage drift n-well and shallow trench isolation layouts on electrical characteristics of LDMOSFETsHuang, C. T.; Tsui, Bing-Yue; Liu, Hsu-Ju; Lin, Geeng-Lih; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009Improvement on ESD Robustness of Lateral DMOS in High-Voltage CMOS ICs by Body Current InjectionChen, Wen-Yi; Ker, Ming-Dou; Jou, Yeh-Ning; Huang, Yeh-Jen; Lin, Geeng-Lih; 電機學院; College of Electrical and Computer Engineering
2008Measurement on Snapback Holding Voltage of High-Voltage LDMOS for Latch-up ConsiderationChen, Wen-Yi; Ker, Ming-Dou; Huang, Yeh-Jen; Jou, Yeh-Ning; Lin, Geeng-Lih; 電機學院; College of Electrical and Computer Engineering
2015Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Latchup-Free ImmunityTang, Kai-Neng; Liao, Seian-Feng; Ker, Ming-Dou; Chiou, Hwa-Chyi; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 7 筆資料，總共 7 筆