高階助聽器晶片及系統---子計畫五：助聽器類比積體電路設計(I)

Abstract

本計畫是「高階助聽器晶片及系統」整合型計劃的一個子計畫。目的是設計及實現此系統所需要的低功率混合訊號式介面電路，並且將與其他數位電路整合於同一晶片上。本計劃將研發（1）類比數位轉換器；（2）數位Class-D喇叭驅動電路；（3）數位電源控制電路。本計畫是延續前一期計畫的研究成果，將發展新技術，改善以上電路的效能。 在麥克風接收端，訊號的頻寬有20 kHz，而訊號的動態範圍（Dynamic Range）可高達100 dB。我們已經研發出新型的Delta-Sigma類比數位轉換器（ADC），配合數位校正技術，可以簡化運算放大器而降低功率消耗。我們將改良此ADC，增進其動態範圍並進一步降低功率消耗。我們會在前端加入可調整增益的放大器（Programmable-Gain Amplifier）來涵蓋麥克風的整個動態範圍。 在喇叭端的驅動電路將會是整個助聽器系統最耗電的部份。我們已經設計了一個高性能的Class-D喇叭驅動電路。我們將嘗試降低Class-D驅動電路的失真度。我們也會針對另一個子計畫所開發的微機電喇叭，設計新的Class-D驅動電路。 本計畫的電源控制電路是從電池擷取能源，並提供穩定的電壓給系統中其他的電路使用。我們提出數位式的電源控制電路，藉以實現複雜的控制機制來提升電路的效能。此電源控制電路需要一個低功率的ADC。我們會用SAR（Successive-Approximation-Register）的架構來實現此ADC。 本計畫的所有電路最後將整合於 90 nm 的 CMOS 單晶片中。以 1 V 電池操作，類比電路的功率消耗不得超過 500 uW。

This project is one of the sub-projects of the “Advanced Hearing Aid SoC and System” project. The objective is to design and realize the essential low-power mixed-signal interface circuits, and then integrate those circuits with other digital circuits on the same chip. This project will develop (1) an audio analog-to-digital converter; (2) a digital class-D speaker driver; and (3) a digital power management circuit. This project is a continuation of a previous research. We will develop new techniques to improve circuit performances. At the microphone end, the required signal bandwidth is 20 kHz and the dynamic range is as high as 100 dB. We have developed a new delta-sigma analog-to-digital converter (ADC) with digital calibration, which was used to reduce the power consumption of the operational amplifiers. We will improve the dynamic range of the existing design while further reducing its power consumption. We will also add a programmable-gain amplifier at the ADC input to cover the entire dynamic range of the microphone. In a hearing aid system, the speaker drivers consume a significant portion of power. We have designed a high-efficient class-D speaker driver. We will further reduce the distortion of the driver. We will also design driver circuits for the MEMS micro speakers developed in a separate sub-project. The power management circuit for this project is to extract energy from a battery and provide stable power supplies for other circuits. We have proposed a new digital power management technique to realize complex control mechanism while improving efficiency. The system requires a low-power ADC, which will be realized using the successive-approximation-register (SAR) architecture. All circuits will be integrated on a single chip fabricated in a 90 nm CMOS technology. Operating under a 1 V battery supply, the total power consumption for the analog circuits will be less than 500 uW.