A High-Speed HBT Prescaler Based on the Divide-by-Two Topology

Abstract

This paper demonstrates the Divide-by4/5 prescalers with merged AND gates in 2 mu m GaInP/GaAs heterojunction bipolar transistor (HBT) and 035 mu m SiGe HBT technologies. By biasing the HBT near the peak transit-time frequency (f(tau)), the maximum operating frequency of a D-type flip-flop (D-FF) can be promoted. At the supply voltage of 5 V, the GaInP/GaAs prescaler operates from 30 MHz to 5.2 GHz, and the SiGe prescaler has the higher-speed performance of 1 GHz similar to 8 GHz at the cost of power consumption.