A High-Speed HBT Prescaler Based on the Divide-by-Two Topology

标题:	A High-Speed HBT Prescaler Based on the Divide-by-Two Topology
作者:	Wei, Hung-Ju Meng, Chinchun Chang, Yuwen Lin, Yi-Chen Huang, Guo-Wei 电信工程研究所 Institute of Communications Engineering
关键字:	GaInP/GaAs HBT;SiGe HBT;Dual-Modulus;Divide-by4/5;Prescaler;Emitter Couple Logic (ECL)
公开日期:	2007
摘要:	This paper demonstrates the Divide-by4/5 prescalers with merged AND gates in 2 mu m GaInP/GaAs heterojunction bipolar transistor (HBT) and 035 mu m SiGe HBT technologies. By biasing the HBT near the peak transit-time frequency (f(tau)), the maximum operating frequency of a D-type flip-flop (D-FF) can be promoted. At the supply voltage of 5 V, the GaInP/GaAs prescaler operates from 30 MHz to 5.2 GHz, and the SiGe prescaler has the higher-speed performance of 1 GHz similar to 8 GHz at the cost of power consumption.
URI:	http://hdl.handle.net/11536/10633
ISBN:	978-1-4244-0748-4
期刊:	2007 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5
起始页:	755
结束页:	758
显示于类别：	Conferences Paper

APA	Wei, H., Meng, C., Chang, Y., Lin, Y., & Huang, G. (2007). High-Speed HBT Prescaler Based on the Divide-by-Two Topology. WOS:000261353300193.
Bibtex	@article{Wei2007High-Speed, title={High-Speed HBT Prescaler Based on the Divide-by-Two Topology}, author={Wei, Hung-Ju and Meng, Chinchun and Chang, Yuwen and Lin, Yi-Chen and Huang, Guo-Wei}, journal={WOS:000261353300193}, year={2007}, url={https://ir.lib.nycu.edu.tw/handle/11536/10633?locale=zh_CN}, }