A Scalable Digitalized Buffer for Gigabit I/O

doi:10.1109/CICC.2008.4672068

標題:	A Scalable Digitalized Buffer for Gigabit I/O
作者:	Lu, HungWen Su, ChauChin Liu, Chien-Nan 交大名義發表 National Chiao Tung University
關鍵字:	Buffer;I/O;SSN
公開日期:	2008
摘要:	A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18 mu m CMOS process, the I/O occupies an area of 0.014mm(2) and operates from 4Gbps@1.9V to 1.5Gbps@1.1V.
URI:	http://dx.doi.org/10.1109/CICC.2008.4672068 http://hdl.handle.net/11536/135105
ISBN:	978-1-4244-2018-6
DOI:	10.1109/CICC.2008.4672068
期刊:	PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE
起始頁:	241
結束頁:	+
Appears in Collections:	Conferences Paper