標題: | Improve Latch-up Immunity by Circuit Solution |
作者: | Tsai, Hui-Wen Ker, Ming-Dou 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2015 |
摘要: | A concept of active guard ring and its corresponding circuit solution to enhance the latch-up immunity of integrated circuits (IC) are proposed and verified in a 0.6-um 5-V CMOS process. By detecting the over-shooting/under-shooting trigger current during latchup current test (I-test), some compensation current generated from on-chip ESD PMOS or NMOS devices through special circuit design can effectively reduce the latchup trigger current that injecting into the core circuit blocks. Therefore, the latchup immunity of I-test with positive or negative trigger current applied at the I/O pins can be significantly improved. |
URI: | http://hdl.handle.net/11536/136115 |
ISBN: | 978-1-4799-9928-6 |
ISSN: | 1946-1550 |
期刊: | PROCEEDINGS OF THE 22ND INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2015) |
起始頁: | 527 |
結束頁: | 530 |
Appears in Collections: | Conferences Paper |