基於佈局之雙單元識別測試產生方法

Abstract

本論文提出了新的雙單元識別故障模型之產生流程，藉以改善之前的雙單元識別故障模型產生流程。而跟之前主要的差別是在於自動化的從目標電路與標準單元庫中抽取有效的雙單元識別故障的方法，利用直接對於電路佈局圖檔案的分析，使得我們不必再使用商業輔助軟體來幫我估算雙單元電路底下的電阻電容值，進而找出可能的故障點；另外也去除了很多我們認為在電路佈局圖上不可能發生而之前卻有對其產生錯誤模型的案件，減少許多不必要的模擬以及之後的測試時間。最後再將我們的錯誤模型透過自動測試圖樣產生來比較我們跟之前的實驗結果。

This thesis proposed a new DCA fault model generate flow to improve the performance of our previous work. We achieve this by changing our method to extract defect in a dual-cell. In this work we do not need to run RC-extraction for every dual-cell pair through the commercial tools anymore, we parsing the cell layout information and find the potential defect to instead. On the other hand, we also proposed a method to delete some defect seems impossibly to happen so we could reduce our simulation time and fault volume. Finally, we generate pattern by commercial ATPG tools to compare our results.