標題: Study of low-temperature and post-stress hysteresis in high-k gate dielectrics
作者: Wu, You-Lin
Lin, Shi-Tin
Yang, Chang Cheng
Wu, Chien-Hung
Chin, Albert
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Jan-2007
摘要: In this work, we present the comparison of hysteresis behaviors of HfAlON and HfSiON high-k dielectrics at low-temperature and subjected to constant voltage stress (CVS). The V-FB instability in the HfAlON and HfSiON gate dielectric were deeply studied. A model is proposed to explain the V-FB Shift and hysteresis direction in thus two samples. We also treat the CVS voltage and CVS time dependence of hysteresis and V-FB Shift. The decreasing hysteresis with temperature is ascribed to traps generation/recombination rate reduction at low temperature.
URI: http://hdl.handle.net/11536/151091
期刊: EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS
起始頁: 653
Appears in Collections:Conferences Paper