標題: Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits
作者: You, Wei-Xiang
Su, Pin
Hu, Chenming
電子工程學系及電子研究所
國際半導體學院
Department of Electronics Engineering and Institute of Electronics
International College of Semiconductor Technology
關鍵字: Dynamic adder;FinFET;Landau-Khalatnikov (L-K) equation;logic circuits;metal-ferroelectric-insulator-semiconductor (MFIS)-type negative-capacitance field-effect transistor (NCFET);NCFET;pass-transistor logic (PTL)
公開日期: 1-Apr-2019
摘要: This paper examines metal-ferroelectric-insulator-semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse V-ds-dependence of threshold voltage (V-T), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low V-DD.
URI: http://dx.doi.org/10.1109/TED.2019.2898445
http://hdl.handle.net/11536/151607
ISSN: 0018-9383
DOI: 10.1109/TED.2019.2898445
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 66
Issue: 4
起始頁: 2004
結束頁: 2009
Appears in Collections:Articles