標題: Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits
作者: Chen, Chun-Cheng
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Active guard ring;electrostatic discharge (ESD) protection;guard ring;latch-up;silicon-controlled rectifier (SCR)
公開日期: 1-Apr-2019
摘要: A new optimization design of an active guard ring has been proposed to improve latch-up immunity of CMOS integrated circuits and been successfully verified in a 0.18-mu m 1.8-/3.3-V CMOS technology. Codesigned with the on-chip electrostatic discharge(ESD) protection devices (gate-ground nMOS and gate-VDD pMOS) equipped at the input-output (I/O) pad, the overshooting/undershooting trigger current during latch-up test can be conducted away through the turned-on channels of the ESD protection MOSFET's to the power rails (V-DD or V-SS). Therefore, the trigger current injecting from the I/O devices (that directly connected to the I/O pad) through the substrate to initiate the latch-up occurrence at the internal circuit blocks can be significantly reduced. Thus, the latch-up immunity of the whole chip can be effectively improved under the same placement distance between the I/O cells and the internal circuit blocks. The new proposed design is a cost-efficient solution to improve latch-up immunity and also to mention good ESD robustness of the I/O cells.
URI: http://dx.doi.org/10.1109/TED.2019.2898317
http://hdl.handle.net/11536/151693
ISSN: 0018-9383
DOI: 10.1109/TED.2019.2898317
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 66
Issue: 4
起始頁: 1648
結束頁: 1655
Appears in Collections:Articles