標題: | A 33-mW 12-bit 100-MHz sample-and-hold amplifier |
作者: | Hsu, CC Wu, JT 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2002 |
摘要: | A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of pre-charging and output capacitor coupling can mitigate the requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 mum CMOS technology, the SHA achieves 73 dB SFDR for 2 Vpp input at 100 MHz sampling rate. The performance is not degraded for input's frequency up to the Nyquist frequency. Power consumption is 33 mW from a single 2.5 V supply. |
URI: | http://hdl.handle.net/11536/18901 |
ISBN: | 0-7803-7363-4 |
期刊: | 2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS |
起始頁: | 169 |
結束頁: | 172 |
顯示於類別: | 會議論文 |