A low-power 1.2GHz 0.35um CMOS PLL

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DC Field	Value	Language
dc.contributor.author	Juang, DC	en_US
dc.contributor.author	Chen, DS	en_US
dc.contributor.author	Shyu, JM	en_US
dc.contributor.author	Wu, CY	en_US
dc.date.accessioned	2014-12-08T15:27:06Z	-
dc.date.available	2014-12-08T15:27:06Z	-
dc.date.issued	2000	en_US
dc.identifier.isbn	0-7803-6470-8	en_US
dc.identifier.uri	http://hdl.handle.net/11536/19327	-
dc.description.abstract	In this paper, a low-power high-speed CMOS PLL is presented. The PLL consists of a 1.2-GHz voltage controlled oscillator, a dead-zone free phase frequency detector, a charge pump, and a frequency divider. The circuit was fabricated using 0.35um TSMC CMOS technology. The total power consumption is 9.6mW at 1.2-GHz operating frequency with 1.5V supply voltage. The phase noise is -94dBc at 10KHz offset.	en_US
dc.language.iso	en_US	en_US
dc.title	A low-power 1.2GHz 0.35um CMOS PLL	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	PROCEEDINGS OF THE SECOND IEEE ASIA PACIFIC CONFERENCE ON ASICS	en_US
dc.citation.spage	99	en_US
dc.citation.epage	102	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000166005300026	-
Appears in Collections:	會議論文