標題: | Novel input ESD protection circuit with substrate-triggering technique in a 0.25-mu m shallow-trench-isolation CMOS technology |
作者: | Ker, MD Chen, TY Wu, CY Tang, H Su, KC Sun, SW 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 1998 |
摘要: | A substrate-triggering technique, to increase the ESD robustness and to reduce the trigger voltage of the ESD protection device, is proposed to improve the ESD-protection efficiency of the input ESD protection circuit in deep-submicron CMOS technology. Through suitable substrate-triggering design on the device structure, this proposed input ESD protection circuit can successfully protect the thinner gate oxide (50 Angstrom) of the input stage in a 0.25-mu m CMOS technology and sustain an ESD level above 2000V without extra process modification. |
URI: | http://hdl.handle.net/11536/19538 |
ISBN: | 0-7803-4455-3 |
期刊: | ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 |
起始頁: | A212 |
結束頁: | A215 |
顯示於類別: | 會議論文 |