標題: | Effect of layout on electromigration characteristics in copper dual damascene interconnects |
作者: | Cheng, Y. L. Chang, Y. M. Leu, Jihperng Bo, T. C. Wang, Y. L. 材料科學與工程學系 Department of Materials Science and Engineering |
關鍵字: | Electromigration;Interconnects;Copper;Layout |
公開日期: | 5-十月-2014 |
摘要: | This study demonstrates that the electromigration (EM) behavior of dual damascene Cu lines is strongly affected by the layout which surrounded the tested EM lines, especially for Cu line below 0.10 mu m used for 40 nm or below technologies. The Cu EM lifetime declines as the number of local dummy lines increase, and the global dummy line density increases with the width of the Cu line below 0.063 mu m. This work presents mechanisms of layout effects that explain the EM characteristics and can be exploited to improve the layout effect. Therefore, not only the stressed Cu line structures, but also the surrounding layouts must to be considered in assessing EM reliability of a real IC circuit in 40 nm or below technology. (C) 2014 Elsevier B.V. All rights reserved. |
URI: | http://dx.doi.org/10.1016/j.mee.2014.05.036 http://hdl.handle.net/11536/24802 |
ISSN: | 0167-9317 |
DOI: | 10.1016/j.mee.2014.05.036 |
期刊: | MICROELECTRONIC ENGINEERING |
Volume: | 128 |
Issue: | |
起始頁: | 19 |
結束頁: | 23 |
顯示於類別: | 期刊論文 |