標題: ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology
作者: Wang, Chang-Tzu
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Bipolar CMOS DMOS (BCD) process;electrostatic discharge (ESD);ESD protection;latchup
公開日期: 1-Dec-2010
摘要: An electrostatic discharge (ESD) protection design for smart power applications with lateral double-diffused MOS (LDMOS) transistors is investigated. With the gate-driven and substrate-triggered circuit techniques, the n-channel LDMOS can be quickly turned on to protect the output drivers during an ESD stress event. The proposed gate-driven and substrate-triggered ESD protection circuits have been successfully verified in a 0.35-mu m 5 V/40 V bipolar CMOS DMOS (BCD) process, which can sustain ESD voltages of 4 kV in human-body-model (HBM) and 275 V in machine-model (MM) ESD tests. In addition, the power-rail ESD protection design can also be achieved with a stacked structure to protect 40-V power pins without a latchup issue in the smart power integrated circuits.
URI: http://dx.doi.org/10.1109/TED.2010.2079530
http://hdl.handle.net/11536/26301
ISSN: 0018-9383
DOI: 10.1109/TED.2010.2079530
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 57
Issue: 12
起始頁: 3395
結束頁: 3404
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