| 標題: | Leakage behavior of the quasi-superlattice stack for multilevel charge storage |
| 作者: | Chang, TC Yan, ST Liu, PT Chen, CW Wu, HH Sze, SM 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| 公開日期: | 3-May-2004 |
| 摘要: | The leakage behavior of the quasi-superlattice structure has been characterized by current-voltage measurements at room temperature and 50 K. A resonant tunnelinglike leakage characteristic is observed at low temperature. The resonant tunneling occurs at around 2, 5.2, and 7 V under a gate voltage swept from 0 to 10 V. A concise physical model is proposed to characterize the leakage mechanism of tunneling for the quasi-lattice structure and suggests that the considerations of the operating voltage for the two-bit per cell nonvolatile-memory device need to be taken into account. (C) 2004 American Institute of Physics. |
| URI: | http://dx.doi.org/10.1063/1.1739514 http://hdl.handle.net/11536/26788 |
| ISSN: | 0003-6951 |
| DOI: | 10.1063/1.1739514 |
| 期刊: | APPLIED PHYSICS LETTERS |
| Volume: | 84 |
| Issue: | 18 |
| 起始頁: | 3687 |
| 結束頁: | 3689 |
| Appears in Collections: | Articles |
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