標題: | Process sensitivity and robustness analysis of via-first dual-damascene process |
作者: | Tsui, BY Chen, CW Huang, SM Lin, SS 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | copper;dual-damascene;interconnections |
公開日期: | 1-五月-2003 |
摘要: | Sacrificial layer (SACL) coating had been proposed to protect the sealing layer of underlying copper lines during trench etching as via-first scheme is employed for dual-damascene patterning. Because the coated SACL thickness depends on via size and via density, the process window is hard to identify. In this paper, the criteria for a successful SACL process are derived. A four-step procedure for SACL process developing is also proposed. It is suggested that shallow trench depth and medium etch rate selectivity between inter-metal-dielectric and SACL material are preferred. The SACL thickness in via can be adjusted by adjusting the overetching percentage at the SACL breakthrough step so that the criteria are satisfied. The validity of the proposed criteria is proved by the very high yield of via chains with via size ranging from 0.27 to 0.16 mum. It is concluded that the SACL process can be robust and can be employed to reduce the thickness of the capping layer effectively even beyond the 0.13-mum technology node. |
URI: | http://dx.doi.org/10.1109/TSM.2003.811887 http://hdl.handle.net/11536/27922 |
ISSN: | 0894-6507 |
DOI: | 10.1109/TSM.2003.811887 |
期刊: | IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING |
Volume: | 16 |
Issue: | 2 |
起始頁: | 307 |
結束頁: | 313 |
顯示於類別: | 期刊論文 |