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dc.contributor.authorWang, CYen_US
dc.contributor.authorTung, SWen_US
dc.contributor.authorJou, JYen_US
dc.date.accessioned2014-12-08T15:41:36Z-
dc.date.available2014-12-08T15:41:36Z-
dc.date.issued2003-01-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCAD.2002.805723en_US
dc.identifier.urihttp://hdl.handle.net/11536/28290-
dc.description.abstractEmbedded cores are being increasingly used in large system-on-a-chip (SoC) designs. The high complexity of SoC designs lead the design verification to be a challenge for system integrators. This paper presents an automatic interconnection rectification (AIR) technique based on the port order fault model to detect, diagnose, and correct the misplacements of interconnection that occurred in the integration of a SoC design automatically. The experiments are conducted on combinational and sequential benchmarks. Experimental results show that the AIR can correct the misplaced interconnection exactly within reasonable efforts and, therefore, accelerates the integration verification of SoC designs.en_US
dc.language.isoen_USen_US
dc.subjectautomatic interconnection rectification (AIR)en_US
dc.subjectcharacteristic vector (CV)en_US
dc.subjectcorrectionen_US
dc.subjectdetectionen_US
dc.subjectdiagnosisen_US
dc.subjectport order fault (POF)en_US
dc.subjectsystem-on-a-chip (SoC)en_US
dc.subjectundetected port sequence (UPS)en_US
dc.subjectverificationen_US
dc.titleAutomatic interconnection rectification for SoC design verification based on the port order fault modelen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCAD.2002.805723en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume22en_US
dc.citation.issue1en_US
dc.citation.spage104en_US
dc.citation.epage114en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000180103600010-
dc.citation.woscount2-
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