完整後設資料紀錄
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dc.contributor.author黃曼珍en_US
dc.contributor.authorMan-Chen Huangen_US
dc.contributor.author陳昌居en_US
dc.contributor.authorChang-Jiu Chenen_US
dc.date.accessioned2014-12-12T01:19:23Z-
dc.date.available2014-12-12T01:19:23Z-
dc.date.issued2007en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009555609en_US
dc.identifier.urihttp://hdl.handle.net/11536/39562-
dc.description.abstract因為SoC領域中,逐漸朝向多核心處理器邁進,因此,傳統用來聯結元件或是系統及處理器的bus已經不敷使用了,利用Torus連結方式可以有效地傳輸資料並提高效能,此外,每個處理器當擁有自己的時脈,必須要有一個全域的時脈來做控制,這樣一來,降低效能且很難設計,在我們的論文中將採用非同步的方式來完成連結網路,利用非同步的連結方式來做溝通,提高效能外,更是一種新的嘗試及挑戰.zh_TW
dc.description.abstractBecause of the slow signal propagation caused by the high wire loads and resistance, the interconnection of SoC cannot be satisfied by the use of a shared bus. A common method of substitution is using unidirectional, point-to-point connections and multiplexers. The Networks on Chip (NoC), due to their characteristics such as scalability, flexibility, high bandwidth, have been proposed as a suitable approach to meet communication requirements in SoC. However, the global clock of the network may cause lots of problems such as clock skew and the design of global clock architecture. Hence, Torus topology was selected to suffice the scalable demands in SoC. We implemented the network with self-timed, cut-through routing approach with one-of-five data encoding. In the experiment, we verify the results of transitions in the interconnection network are correct and our system should operate at 63.9MHz. Today, the multi-core systems are produced in SoC; we can use our network to communicate between them and resolve some clock problems efficiently.en_US
dc.language.isoen_USen_US
dc.subject非同步zh_TW
dc.subject1-of-5編碼zh_TW
dc.subject連結網路zh_TW
dc.subjectAsynchronousen_US
dc.subject1-of-5 encodingen_US
dc.subjectTorusen_US
dc.title自時花托連結網路利用一五編碼方式zh_TW
dc.titleSelf-Timed Torus Interconnection Network with one-of-five encodingen_US
dc.typeThesisen_US
dc.contributor.department資訊科學與工程研究所zh_TW
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