標題: 多重奈米通道複晶矽薄膜電晶體之製造與特性研究
Fabrication and Characterization of Polysilicon Thin Film Transistors with Multiple Nano-wire Channels
作者: 陳稚軒
Chi-Shen Chen
施敏
張鼎張
S.M. Sze
Ting-Chang Chang
電子研究所
關鍵字: 多重奈米通道;複晶矽薄膜電晶體;poly-Si TFTs;multiple nano-wire channels
公開日期: 2003
摘要: 本研究主要是在探討具有輕參雜(LDD)與多重通道(multiple channels)結構的複晶矽薄膜電晶體(poly-Si TFTs),在具有不同通道寬度和數目下,閘極控制能力的好壞,與可靠度的研究。LDD本身具有降低漏電流的效應,結合上十條奈米導線通道的薄膜電晶體,展現出較其他通道數目和寬度的TFT,較佳且較穩定的電性。如較高的開關電流比(>108),較陡峭的次臨界導通斜率(SS),較小的汲極導致能障下降 (DIBL),較佳的糾結效應(kink-effect)抑制能力,與較佳的製程穩定度。原因是M10有最佳的閘極控制能力,及較好的電漿保護效應。由一系列的實驗結果發現,閘極的控制能力是隨著通道數目的增加而變強。此外在可靠度的研究中,M10的薄膜電晶體展現佳的抗stress的能力,M10的臨界電壓和次臨界導通斜率幾乎不隨stress時間而改變。因此這種控制能力佳、高效能、高可靠度,且不需額外製程的新穎結構之TFT,將可被廣泛的運用在主動式矩陣液晶顯示器(AMLCD)上
We have studied the gate controllability of lightly-doped drain (LDD) polycrystalline silicon thin-film transistors (poly-Si TFTs) with multiple channels and different widths. We deserve that devices with an LDD structure exhibit low leakage current. Additionally, the poly-Si TFT (M10) with ten strips multiple nano-wire channels exhibits the best and the most stable electrical characteristics than all other structures we have studied, such as a higher ON/OFF current ratio (>108), a steeper subthreshold slope (SS, 110 mV/decade), an absence of drain-induced barrier lowering (DIBL), and a improved suppressed kink-effect. Experiments results show the gate controllability is increasing with channel number from single channel to ten strips multiple channels. The M10 TFT also shows the best stress characteristics, as Vth and SS of the M10 TFT remain constant before and after the stress. Devices with the proposed TFTs are highly promising for use in active-matrix liquid-crystal-display technologies without any additional processes.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009111560
http://hdl.handle.net/11536/43235
顯示於類別:畢業論文


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