| 標題: | A NEW STRUCTURE-ORIENTED MODEL FOR WELL RESISTANCE IN CMOS LATCHUP STRUCTURES |
| 作者: | CHEN, MJ SZE, SC CHEN, HH WU, CY 交大名義發表 工學院 National Chiao Tung University College of Engineering |
| 公開日期: | 1-Apr-1987 |
| URI: | http://hdl.handle.net/11536/4651 |
| ISSN: | 0018-9383 |
| 期刊: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
| Volume: | 34 |
| Issue: | 4 |
| 起始頁: | 890 |
| 結束頁: | 897 |
| Appears in Collections: | Articles |
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- Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs / Hsu, Sheng-Fu;Ker, Ming-Dou
- 深次微米CMOS時間介電崩潰及鎖定之研究 / 陳志輝;Chen, Zhi-Hui;陳明哲;Chen, Ming-Zhe
- Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology / Ker, MD;Lo, WY
- TRANSIENT ANALYSIS OF SUBMICRON CMOS LATCHUP WITH A PHYSICAL CRITERION / KER, MD;WU, CY
- A NEW CRITERION FOR TRANSIENT LATCHUP ANALYSIS IN BULK CMOS / YANG, YH;WU, CY
- A STRUCTURE-ORIENTED MODEL FOR DETERMINING THE SUBSTRATE SPREADING RESISTANCE IN BULK CMOS LATCH-UP PATHS AND ITS APPLICATION IN HOLDING CURRENT PREDICTION / CHEN, MJ;WU, CY
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