| 標題: | AN EFFICIENT METHOD FOR CALCULATING THE DC TRIGGERING CURRENTS IN CMOS LATCH-UP |
| 作者: | CHEN, MJ WU, CY 交大名義發表 工學院 National Chiao Tung University College of Engineering |
| 公開日期: | 1-May-1986 |
| URI: | http://hdl.handle.net/11536/4751 |
| ISSN: | 0038-1101 |
| 期刊: | SOLID-STATE ELECTRONICS |
| Volume: | 29 |
| Issue: | 5 |
| 起始頁: | 551 |
| 結束頁: | 554 |
| Appears in Collections: | Articles |
- Component-level measurement for transient-induced latch-up in CMOS ICs under system-level ESD considerations / Ker, Ming-Dou;Hsu, Sheng-Fu
- Active Guard Ring to Improve Latch-Up Immunity / Tsai, Hui-Wen;Ker, Ming-Dou
- A reverse-voltage protection circuit for MOSFET power switches / Hong, HP;Wu, JC
- 高壓BCD製程之靜電放電防護元件設計與實現 / 許哲綸;Hsu, Che-Lun;柯明道;Ker, Ming-Dou
- Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits / Chen, Chun-Cheng;Ker, Ming-Dou
- SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes / Ker, MD;Hsu, KC
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