三維積體電路關鍵技術之矽穿孔導線研究

Abstract

本論文為研究三維積體關鍵技術之一的矽穿孔導線。三維積體電路技術乃是使用矽穿孔導線製作在薄化晶圓上，透過接合技術進行晶圓堆疊接合，可將傳統二維積體電路轉成三維積體電路，有效的利用空間並縮短電流訊號所流通的距離、降低電阻電容所造成的延遲時間及功率損失。 矽穿孔的製作採用感應式電漿蝕刻機機台，使用的方法為BOSCH深反應性離子蝕刻。此技術採取三段式蝕刻分別為鈍化層沉積、非等向性離子撞擊和等向性反應蝕刻，這樣的技術本身可以達到高深寬比的孔洞，但如果機台的內部參數沒有進行優化，則可能就會造成矽穿孔底部出現微米草或是扇貝狀的側壁蝕刻形貌，這樣都會使得薄膜沉積及電鍍出現問題，因此本論文針對蝕刻做了內部參數的調整及研究。當矽穿孔製作完成後，接著進行絕緣層、附著層、防擴散層和晶種層沉積。晶種層的選擇關係到電鍍液選取，也影響到矽穿孔導線的特性。本論文基於使用普遍性及良好的導電率的原因，選擇銅做為矽穿孔的填充。 論文的第二部分提出一種新穎方式來製作矽穿孔導線。此方法為自底而上電鍍法的改良方式。自底而上電鍍法有幾個相當吸引人的特點：如電鍍不受深寬比影響、不需要電鍍添加液(如加速液、抑止液、平整液)也能達到無孔洞的電鍍、電鍍機台採用PCB機台就可完成等好處；但也有缺點如製程步驟過多或是移除機制缺乏等等問題。因此本論文提出改良型的自底而上電鍍法，這樣方法的核心價值為改變矽穿孔導線及微米焊點的製作順序:先製作出微米焊點再做出矽穿孔導線，這樣可以減少一道光罩以及一道沉積過程。另外此法無須使用載片，所以沒有移除載片困難的問題。製作過程中使用光學顯微鏡、掃描式電子顯微鏡、X光斷層掃描和能量散佈分析儀以進行材料及製程分析。電性分析之結果包括單根矽穿孔導線電阻值、多根矽穿孔導線電阻值、多根矽穿孔導線漏電值和多根矽穿孔導線耦合電容值，上述的電性分析都展現優越結果，更加確定此架構的可行性。

This thesis focuses on researches of through silicon via (TSV) in three-dimension integrated circuits (3D-IC). In simple terms, the technologies of three-dimensional integrated circuit include the use of TSV, wafer thinning process, and bonding technology for chip-to-chip, chip-to-wafer, or wafer-to-wafer stacking. Therefore, conventional two-dimensional integrated circuits can be fabricated in the format of three-dimensional. 3D-IC can effectively use spaces, reduce the distance of current signal, and decrease constant delay time and power losses. In this thesis, TSV formation uses Bosch reactive ion etching by inductive couple plasma etcher. Bosch etching contains three steps of the rapid transformation: surface passivation by polymer gas (C4F8), Argon ion bombardment anisotropic etching by Argon ion bombardment, and isotropic etching (SF6). The three-step etching mechanism can achieve a high aspect ratio etching. However, if the parameter is not optimized, issues such as micro-grass, sidewall etching, and scallops may occur. Finally, no micro-grass and smooth sidewall of TSV was fabricated by insulation layer, adhesive layer, barrier layer, seed layer deposition, and Cu plating. In the second part of this thesis, one novel TSV fabrication method is proposed. This method is based on bottom-up plating, which has several attractive features, including independent TSV aspect ratio with electroplating process, no additives (accelerator, suppressor, and leveler) required in electroplating solution for super-filling, and PCB electroplating process compatible for fast and void-free bottom-up filling. However, this method also includes some drawbacks, such as many process steps, and shortage of removal mechanism. Therefore, the improved bottom-up plating method, defined as “sealing bump bottom-up plating”, can change the process order of TSV and micro-bump formation by first sealing micro-bump formation and then using bump-up plating to form TSV. As a result, this new process can reduce one process and one step of lithography compared to the conventional one. In addition, this process does not require the carrier wafer thus the removal issue can be avoided. This method has been successfully demonstrated in chip-level with 25, 50, 75, and 100 □m TSVs and 200 □m thinned wafers. With OM, EDX, SEM and X-ray analysis, no defects were observed inside these TSVs. Finally, Kelvin structure, daisy chain, and comb structure were fabricated for electrical measurements of single TSV resistance, multiple TSV resistance, multiple TSV leakage, and multiple TSV coupling capacitances. Excellent electrical performances were shown in these measurements.