標題: | 低功率互補式金氧半射頻前端接收器-使用堆疊式低雜訊放大器及混頻器 Low-Power CMOS RF Receiver Front-End With Stacked LNA-Mixer |
作者: | 吳柏霖 Pao-Lin Wu 謝太烱 Tai-Chiung Hsieh 電子物理系所 |
關鍵字: | 射頻積體電路;接收機;低雜訊放大器;混頻器;低功率;RFIC;Receiver;LNA;Mixer;Low-Power |
公開日期: | 2003 |
摘要: | 由於接收器前端電路是高耗電裝置且可攜式通訊設備具有限的電源,因而在射頻段低功率操作的可攜式應用引發了很廣泛的研究。
基於電流再利用的觀點,此論文提出了一個使用堆疊式低雜訊放大器及混頻器的低功率射頻接收器,其中採用了台灣積體電路製造股份有限公司提供的0.18-μm互補式金氧半製程技術。此堆疊式低雜訊放大器及混頻器是設計用來作為一應用於藍芽系統的積體化低中頻映像消除接收器的第一級電路。此電路的模擬和佈局圖已經完成。
模擬結果顯示,所設計的堆疊式低雜訊放大器及混頻器可在1.8 V電源下正常工作。此堆疊式低雜訊放大器及混頻器僅消耗6.3 mW功率。本地震盪器的功率要求是在2.38 GHz頻段要有-5 dBm。此全級電路的轉換增益為24.4 dB,當中頻為40 MHz時,其雜訊指數為3.8 dB,輸入1-dB增益壓縮點為-29 dBm,輸入三階截點為-20.5 dBm。整個堆疊式低雜訊放大器及混頻器佔有晶片面積為1.5mm × 1.2mm。 Owing to receiver front-end circuits are power-hungry blocks and portable communication devices are usually battery-limited, hence, the demand for low-power operations in portable applications has led to extensive research on RF circuit design. In this thesis, based on current-reuse concept, we present a low-power RF receiver front-end with stacked LNA-Mixer by TSMC (Taiwan Semiconductors Manufacture Company) 0.18-μm 1P6M CMOS technology. This stacked LNA-Mixer is designed as the first stage of an integrated low-IF image-reject receiver under development for Bluetooth applications. The circuit simulations and layout of stacked LNA-Mixer are carried out. Simulation results reveal that the proposed stacked LNA-Mixer can operate well under 1.8 V power supply. The stacked LNA-Mixer circuit only consumes 6.3 mW. LO available power requirement is -5 dBm at 2.38 GHz frequency band. The conversion gain of overall circuit is about 24.4 dB. Noise figure is about 3.8 dB at 40 MHz IF. Input 1-dB gain compression point is -29 dBm while IIP3 point is at -20.5 dBm. The entire stacked LNA-Mixer occupies a die area of 1.5mm × 1.2mm. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009121536 http://hdl.handle.net/11536/52101 |
Appears in Collections: | Thesis |
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